[x265] [PATCH] asm-avx2: filter_vpp[32x24, 32x16, 32x8], filter_vps[32x24, 32x16, 32x8]

[Divya Manivannan]

# HG changeset patch
# User Divya Manivannan <divya at multicorewareinc.com>
# Date 1425537677 -19800
#      Thu Mar 05 12:11:17 2015 +0530
# Node ID a37b832166e0ac9dca80eeca8cdff7ae90ec60fa
# Parent  ea9bdb10353fcb06cea1045ba0186c22c448df63
asm-avx2: filter_vpp[32x24, 32x16, 32x8], filter_vps[32x24, 32x16, 32x8]

filter_vpp[32x24, 32x16, 32x8]: 2813c->1442c, 1893c->988c, 1021c->557c
filter_vps[32x24, 32x16, 32x8]: 2837c->1798c, 2059c->1281c, 1001c->643c

diff -r ea9bdb10353f -r a37b832166e0 source/common/x86/asm-primitives.cpp
--- a/source/common/x86/asm-primitives.cpp	Wed Mar 04 13:20:55 2015 +0530
+++ b/source/common/x86/asm-primitives.cpp	Thu Mar 05 12:11:17 2015 +0530
@@ -1589,9 +1589,15 @@
 
         p.chroma[X265_CSP_I420].pu[CHROMA_420_16x16].filter_vpp = x265_interp_4tap_vert_pp_16x16_avx2;
         p.chroma[X265_CSP_I420].pu[CHROMA_420_32x32].filter_vpp = x265_interp_4tap_vert_pp_32x32_avx2;
+        p.chroma[X265_CSP_I420].pu[CHROMA_420_32x24].filter_vpp = x265_interp_4tap_vert_pp_32x24_avx2;
+        p.chroma[X265_CSP_I420].pu[CHROMA_420_32x16].filter_vpp = x265_interp_4tap_vert_pp_32x16_avx2;
+        p.chroma[X265_CSP_I420].pu[CHROMA_420_32x8].filter_vpp = x265_interp_4tap_vert_pp_32x8_avx2;
 
         p.chroma[X265_CSP_I420].pu[CHROMA_420_16x16].filter_vps = x265_interp_4tap_vert_ps_16x16_avx2;
         p.chroma[X265_CSP_I420].pu[CHROMA_420_32x32].filter_vps = x265_interp_4tap_vert_ps_32x32_avx2;
+        p.chroma[X265_CSP_I420].pu[CHROMA_420_32x24].filter_vps = x265_interp_4tap_vert_ps_32x24_avx2;
+        p.chroma[X265_CSP_I420].pu[CHROMA_420_32x16].filter_vps = x265_interp_4tap_vert_ps_32x16_avx2;
+        p.chroma[X265_CSP_I420].pu[CHROMA_420_32x8].filter_vps = x265_interp_4tap_vert_ps_32x8_avx2;
 #else
         /* functions with both 64-bit and 32-bit implementations */
         p.cu[BLOCK_4x4].dct = x265_dct4_avx2;
diff -r ea9bdb10353f -r a37b832166e0 source/common/x86/ipfilter8.asm
--- a/source/common/x86/ipfilter8.asm	Wed Mar 04 13:20:55 2015 +0530
+++ b/source/common/x86/ipfilter8.asm	Thu Mar 05 12:11:17 2015 +0530
@@ -5344,10 +5344,10 @@
 FILTER_V4_W32 32, 48
 FILTER_V4_W32 32, 64
 
-%macro FILTER_VER_CHROMA_AVX2_32x32 1
+%macro FILTER_VER_CHROMA_AVX2_32xN 2
 INIT_YMM avx2
 %if ARCH_X86_64 == 1
-cglobal interp_4tap_vert_%1_32x32, 4, 7, 13
+cglobal interp_4tap_vert_%1_32x%2, 4, 7, 13
     mov             r4d, r4m
     shl             r4d, 6
 
@@ -5369,7 +5369,7 @@
     vbroadcasti128  m12, [pw_2000]
 %endif
     lea             r5, [r3 * 3]
-    mov             r6d, 8
+    mov             r6d, %2 / 4
 .loopW:
     movu            m0, [r0]                        ; m0 = row 0
     movu            m1, [r0 + r1]                   ; m1 = row 1
@@ -5476,8 +5476,14 @@
 %endif
 %endmacro
 
-FILTER_VER_CHROMA_AVX2_32x32 pp
-FILTER_VER_CHROMA_AVX2_32x32 ps
+FILTER_VER_CHROMA_AVX2_32xN pp, 32
+FILTER_VER_CHROMA_AVX2_32xN pp, 24
+FILTER_VER_CHROMA_AVX2_32xN pp, 16
+FILTER_VER_CHROMA_AVX2_32xN pp, 8
+FILTER_VER_CHROMA_AVX2_32xN ps, 32
+FILTER_VER_CHROMA_AVX2_32xN ps, 24
+FILTER_VER_CHROMA_AVX2_32xN ps, 16
+FILTER_VER_CHROMA_AVX2_32xN ps, 8
 
 ;-----------------------------------------------------------------------------
 ; void interp_4tap_vert_pp_%1x%2(pixel *src, intptr_t srcStride, pixel *dst, intptr_t dstStride, int coeffIdx)