[x265] [PATCH] chroma_hps[4x4] for i420 avx2 asm: 336c->214c

[chen]

At 2015-03-09 18:36:13,aasaipriya at multicorewareinc.com wrote:
># HG changeset patch
># User Aasaipriya Chandran <aasaipriya at multicorewareinc.com>
># Date 1425897362 -19800
>#      Mon Mar 09 16:06:02 2015 +0530
># Node ID 06b67c917202b50c2aa7f4f5c4e0cf7f94b56145
># Parent  04861917b7b343216ac1b9a9f70e38396af53275
>chroma_hps[4x4] for i420 avx2 asm: 336c->214c
>
>diff -r 04861917b7b3 -r 06b67c917202 source/common/x86/asm-primitives.cpp
>--- a/source/common/x86/asm-primitives.cpp	Thu Feb 26 19:11:18 2015 +0530
>+++ b/source/common/x86/asm-primitives.cpp	Mon Mar 09 16:06:02 2015 +0530
>@@ -1791,6 +1791,8 @@
>         p.chroma[X265_CSP_I420].pu[CHROMA_420_32x32].filter_hpp = x265_interp_4tap_horiz_pp_32x32_avx2;
>         p.chroma[X265_CSP_I420].pu[CHROMA_420_16x16].filter_hpp = x265_interp_4tap_horiz_pp_16x16_avx2;
> 
>+        p.chroma[X265_CSP_I420].pu[CHROMA_420_4x4].filter_hps = x265_interp_4tap_horiz_ps_4x4_avx2;
>+
>         p.pu[LUMA_4x4].luma_vps = x265_interp_8tap_vert_ps_4x4_avx2;
> 
>         p.pu[LUMA_4x4].luma_vpp = x265_interp_8tap_vert_pp_4x4_avx2;
>diff -r 04861917b7b3 -r 06b67c917202 source/common/x86/ipfilter8.asm
>--- a/source/common/x86/ipfilter8.asm	Thu Feb 26 19:11:18 2015 +0530
>+++ b/source/common/x86/ipfilter8.asm	Mon Mar 09 16:06:02 2015 +0530
>@@ -1719,6 +1719,90 @@
>     IPFILTER_LUMA_64x_avx2 64 , 32
>     IPFILTER_LUMA_64x_avx2 64 , 16
> 
>+
>+;-----------------------------------------------------------------------------------------------------------------------------
>+; void interp_4tap_horiz_ps_4x4(pixel *src, intptr_t srcStride, int16_t *dst, intptr_t dstStride, int coeffIdx, int isRowExt)
>+;-----------------------------------------------------------------------------------------------------------------------------;
>+INIT_YMM avx2 
>+cglobal interp_4tap_horiz_ps_4x4, 4,7,5
>+    mov             r4d, r4m
>+    mov             r5d, r5m
>+    add             r3d, r3d
>+
>+%ifdef PIC
>+    lea               r6,           [tab_ChromaCoeff]
>+    vpbroadcastd      m0,           [r6 + r4 * 4]
>+%else
>+    vpbroadcastd      m0,           [tab_ChromaCoeff + r4 * 4]
>+%endif
>+
>+    vbroadcasti128     m2,           [pw_1]
>+    vbroadcasti128     m1,           [tab_Tm]
>+
>+    ; register map
>+    ; m0 - interpolate coeff
>+    ; m1 - shuffle order table
>+    ; m2 - constant word 1
>+
>+    dec                r0
>+    cmp                r5d, byte 0


test r5d,r5d

if you move this conditional statement to above, you may reuse r5 and reduce r6.

becareful, the dec will broken flag register.

 

>+    je                 .label
>+    sub                r0 , r1
>+
>+.label
>+    ; Row 0-1
>+    vbroadcasti128    m3,           [r0]                        ; [x x x x x A 9 8 7 6 5 4 3 2 1 0]
>+    vinserti128       m3,           m3,      [r0 + r1],     1

in the Intel docs, it is Exception 6, maybe need aligned address
Of course, it work fine on Haswell platform.
 
>+    pshufb            m3,           m1
>+    pmaddubsw         m3,           m0
>+    pmaddwd           m3,           m2
>+
>+    ; Row 2-3
>+    lea               r0,           [r0 + r1 * 2]
>+    vbroadcasti128    m4,           [r0]                      ; [x x x x x A 9 8 7 6 5 4 3 2 1 0]
>+    vinserti128       m4,           m4,      [r0 + r1],     1
>+    pshufb            m4,           m1
>+    pmaddubsw         m4,           m0
>+    pmaddwd           m4,           m2
>+
>+    packssdw          m3,           m4
>+    psubw             m3,           [pw_2000]
>+    vextracti128      xm4,          m3,     1
>+    movq              [r2],         xm3
>+    movq              [r2+r3],      xm4
>+    lea               r2,           [r2 + r3 * 2]
>+    movhps            [r2],         xm3
>+    movhps            [r2 + r3],    xm4
>+
>+    cmp                r5d,           byte 0
>+    jz                .end
>+    lea               r2,           [r2 + r3 * 2]
>+    lea               r0,           [r0 + r1 * 2]
>+
>+    ;Row 5-6
>+    vbroadcasti128    m3,           [r0]                        ; [x x x x x A 9 8 7 6 5 4 3 2 1 0]
>+    vinserti128       m3,           m3,      [r0 + r1],     1
>+    pshufb            m3,           m1
>+    pmaddubsw         m3,           m0
>+    pmaddwd           m3,           m2
>+
>+    ; Row 7
>+    lea               r0,           [r0 + r1 * 2]
>+    vbroadcasti128    m4,           [r0]                      ; [x x x x x A 9 8 7 6 5 4 3 2 1 0]
>+    pshufb            m4,           m1
>+    pmaddubsw         m4,           m0
>+    pmaddwd           m4,           m2
>+
>+    packssdw          m3,           m4
>+    psubw             m3,           [pw_2000]
>+
>+    vextracti128      xm4,          m3,     1
>+    movq              [r2],         xm3
>+    movq              [r2+r3],      xm4
>+    lea               r2,           [r2 + r3 * 2]
>+    movhps            [r2],         xm3
>+.end
>+   RET
> ;-----------------------------------------------------------------------------------------------------------------------------
> ;void interp_horiz_ps_c(const pixel* src, intptr_t srcStride, int16_t* dst, intptr_t dstStride, int coeffIdx, int isRowExt)
> ;-----------------------------------------------------------------------------------------------------------------------------
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