[x265] [PATCH] asm: intra_pred_ang8_22

[praveen at multicorewareinc.com]

# HG changeset patch
# User Praveen Tiwari <praveen at multicorewareinc.com>
# Date 1425989753 -19800
# Node ID 62dcfcba14e59543f92752c8145c612e13af472f
# Parent  fc805c02d0f28815e86e65c2f6d0bfea69db0f7b
asm: intra_pred_ang8_22

diff -r fc805c02d0f2 -r 62dcfcba14e5 source/common/x86/asm-primitives.cpp
--- a/source/common/x86/asm-primitives.cpp	Tue Mar 10 14:01:26 2015 +0530
+++ b/source/common/x86/asm-primitives.cpp	Tue Mar 10 17:45:53 2015 +0530
@@ -1499,6 +1499,7 @@
         p.cu[BLOCK_8x8].intra_pred[11] = x265_intra_pred_ang8_11_avx2;
         p.cu[BLOCK_8x8].intra_pred[12] = x265_intra_pred_ang8_12_avx2;
         p.cu[BLOCK_8x8].intra_pred[24] = x265_intra_pred_ang8_24_avx2;
+        p.cu[BLOCK_8x8].intra_pred[22] = x265_intra_pred_ang8_22_avx2;
 
         // copy_sp primitives
         p.cu[BLOCK_16x16].copy_sp = x265_blockcopy_sp_16x16_avx2;
diff -r fc805c02d0f2 -r 62dcfcba14e5 source/common/x86/intrapred.h
--- a/source/common/x86/intrapred.h	Tue Mar 10 14:01:26 2015 +0530
+++ b/source/common/x86/intrapred.h	Tue Mar 10 17:45:53 2015 +0530
@@ -182,6 +182,7 @@
 void x265_intra_pred_ang8_11_avx2(pixel* dst, intptr_t dstStride, const pixel* srcPix, int dirMode, int bFilter);
 void x265_intra_pred_ang8_12_avx2(pixel* dst, intptr_t dstStride, const pixel* srcPix, int dirMode, int bFilter);
 void x265_intra_pred_ang8_24_avx2(pixel* dst, intptr_t dstStride, const pixel* srcPix, int dirMode, int bFilter);
+void x265_intra_pred_ang8_22_avx2(pixel* dst, intptr_t dstStride, const pixel* srcPix, int dirMode, int bFilter);
 void x265_all_angs_pred_4x4_sse4(pixel *dest, pixel *refPix, pixel *filtPix, int bLuma);
 void x265_all_angs_pred_8x8_sse4(pixel *dest, pixel *refPix, pixel *filtPix, int bLuma);
 void x265_all_angs_pred_16x16_sse4(pixel *dest, pixel *refPix, pixel *filtPix, int bLuma);
diff -r fc805c02d0f2 -r 62dcfcba14e5 source/common/x86/intrapred8.asm
--- a/source/common/x86/intrapred8.asm	Tue Mar 10 14:01:26 2015 +0530
+++ b/source/common/x86/intrapred8.asm	Tue Mar 10 17:45:53 2015 +0530
@@ -132,6 +132,11 @@
 %assign x x+1
 %endrep
 
+c_ang8_mode_22:       db 13, 19, 13, 19, 13, 19, 13, 19, 13, 19, 13, 19, 13, 19, 13, 19, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, \
+                         7, 25, 7, 25, 7, 25, 7, 25, 7, 25, 7, 25, 7, 25, 7, 25, 20, 12, 20, 12, 20, 12, 20, 12, 20, 12, 20, 12, 20, 12, 20, 12,\
+                         1, 31, 1, 31, 1, 31, 1, 31, 1, 31, 1, 31, 1, 31, 1, 31, 14, 18, 14, 18, 14, 18, 14, 18, 14, 18, 14, 18, 14, 18, 14, 18, \
+                         27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 8, 24, 8, 24, 8, 24, 8, 24, 8, 24, 8, 24, 8, 24, 8, 24
+
 SECTION .text
 
 cextern pw_2
@@ -10451,3 +10456,58 @@
     movq              [r0 + 2 * r1], xm2
     movhps            [r0 + r3], xm2
     RET
+
+INIT_YMM avx2
+cglobal intra_pred_ang8_22, 3, 5, 6
+    mova              m3, [pw_1024]
+    vbroadcasti128    m0, [r2]
+    pshufb            m0, [intra_pred_shuff_0_8]
+    lea               r4, [c_ang8_mode_22]
+
+    ; Row [0, 1] 
+    pmaddubsw         m1, m0, [r4]
+    pmulhrsw          m1, m3
+
+    ; Row [2, 3]
+    vextracti128      xm5, m0, 0
+    pslldq            xm5, 2
+    pinsrb            xm5, [r2 + 16 + 2], 0
+    pinsrb            xm5, [r2 + 0], 1
+    vinserti128       m0, m5, xm5, 1
+    pmaddubsw         m2, m0, [r4 + mmsize]
+    pmulhrsw          m2, m3
+
+    ; Row [4, 5]
+    vextracti128      xm5, m0, 0
+    pslldq            xm5, 2
+    pinsrb            xm5, [r2 + 16 + 5], 0
+    pinsrb            xm5, [r2 + 16 + 2], 1
+    vinserti128       m0, m5, xm5, 1
+    pmaddubsw         m4, m0, [r4 + 2 * mmsize]
+    pmulhrsw          m4, m3
+
+    ; Row [6, 7]
+    vextracti128      xm5, m0, 0
+    pslldq            xm5, 2
+    pinsrb            xm5, [r2 + 16 + 7], 0
+    pinsrb            xm5, [r2 + 16 + 5], 1
+    vinserti128       m0, m0, xm5, 1
+    pmaddubsw         m0, [r4 + 3 * mmsize]
+    pmulhrsw          m0, m3
+
+    packuswb          m1, m2
+    packuswb          m4, m0
+
+    lea               r3, [3 * r1]
+    movq              [r0], xm1
+    vextracti128      xm2, m1, 1
+    movq              [r0 + r1], xm2
+    movhps            [r0 + 2 * r1], xm1
+    movhps            [r0 + r3], xm2
+    lea               r0, [r0 + 4 * r1]
+    movq              [r0], xm4
+    vextracti128      xm2, m4, 1
+    movq              [r0 + r1], xm2
+    movhps            [r0 + 2 * r1], xm4
+    movhps            [r0 + r3], xm2
+    RET