[x265] [PATCH 1 of 4] asm: filter_vsp[4x8], filter_vss[4x8] in avx2: 673c->339c, 608c->263c
Divya Manivannan
divya at multicorewareinc.com
Mon Mar 16 05:54:50 CET 2015
# HG changeset patch
# User Divya Manivannan <divya at multicorewareinc.com>
# Date 1426480831 -19800
# Mon Mar 16 10:10:31 2015 +0530
# Node ID 1a75e47e72c6d3ffb8554c4f7c463d88bfefa294
# Parent 6461985f33ac6fc5b205879bbb0f2a535226ca76
asm: filter_vsp[4x8], filter_vss[4x8] in avx2: 673c->339c, 608c->263c
diff -r 6461985f33ac -r 1a75e47e72c6 source/common/x86/asm-primitives.cpp
--- a/source/common/x86/asm-primitives.cpp Sun Mar 15 11:58:32 2015 -0500
+++ b/source/common/x86/asm-primitives.cpp Mon Mar 16 10:10:31 2015 +0530
@@ -1653,6 +1653,7 @@
p.chroma[X265_CSP_I420].pu[CHROMA_420_8x8].filter_vsp = x265_interp_4tap_vert_sp_8x8_avx2;
p.chroma[X265_CSP_I420].pu[CHROMA_420_16x16].filter_vsp = x265_interp_4tap_vert_sp_16x16_avx2;
p.chroma[X265_CSP_I420].pu[CHROMA_420_32x32].filter_vsp = x265_interp_4tap_vert_sp_32x32_avx2;
+ p.chroma[X265_CSP_I420].pu[CHROMA_420_4x8].filter_vsp = x265_interp_4tap_vert_sp_4x8_avx2;
p.chroma[X265_CSP_I420].pu[CHROMA_420_16x32].filter_vsp = x265_interp_4tap_vert_sp_16x32_avx2;
p.chroma[X265_CSP_I420].pu[CHROMA_420_24x32].filter_vsp = x265_interp_4tap_vert_sp_24x32_avx2;
p.chroma[X265_CSP_I420].pu[CHROMA_420_32x16].filter_vsp = x265_interp_4tap_vert_sp_32x16_avx2;
@@ -1661,6 +1662,7 @@
p.chroma[X265_CSP_I420].pu[CHROMA_420_8x8].filter_vss = x265_interp_4tap_vert_ss_8x8_avx2;
p.chroma[X265_CSP_I420].pu[CHROMA_420_16x16].filter_vss = x265_interp_4tap_vert_ss_16x16_avx2;
p.chroma[X265_CSP_I420].pu[CHROMA_420_32x32].filter_vss = x265_interp_4tap_vert_ss_32x32_avx2;
+ p.chroma[X265_CSP_I420].pu[CHROMA_420_4x8].filter_vss = x265_interp_4tap_vert_ss_4x8_avx2;
p.chroma[X265_CSP_I420].pu[CHROMA_420_16x32].filter_vss = x265_interp_4tap_vert_ss_16x32_avx2;
p.chroma[X265_CSP_I420].pu[CHROMA_420_24x32].filter_vss = x265_interp_4tap_vert_ss_24x32_avx2;
p.chroma[X265_CSP_I420].pu[CHROMA_420_32x16].filter_vss = x265_interp_4tap_vert_ss_32x16_avx2;
diff -r 6461985f33ac -r 1a75e47e72c6 source/common/x86/ipfilter8.asm
--- a/source/common/x86/ipfilter8.asm Sun Mar 15 11:58:32 2015 -0500
+++ b/source/common/x86/ipfilter8.asm Mon Mar 16 10:10:31 2015 +0530
@@ -12788,6 +12788,118 @@
FILTER_VER_CHROMA_S_AVX2_4x4 sp
FILTER_VER_CHROMA_S_AVX2_4x4 ss
+%macro FILTER_VER_CHROMA_S_AVX2_4x8 1
+INIT_YMM avx2
+cglobal interp_4tap_vert_%1_4x8, 4, 6, 8
+ mov r4d, r4m
+ shl r4d, 6
+ add r1d, r1d
+ sub r0, r1
+
+%ifdef PIC
+ lea r5, [pw_ChromaCoeffV]
+ add r5, r4
+%else
+ lea r5, [pw_ChromaCoeffV + r4]
+%endif
+
+ lea r4, [r1 * 3]
+%ifidn %1,sp
+ mova m7, [pd_526336]
+%else
+ add r3d, r3d
+%endif
+
+ movq xm0, [r0]
+ movq xm1, [r0 + r1]
+ punpcklwd xm0, xm1
+ movq xm2, [r0 + r1 * 2]
+ punpcklwd xm1, xm2
+ vinserti128 m0, m0, xm1, 1 ; m0 = [2 1 1 0]
+ pmaddwd m0, [r5]
+ movq xm3, [r0 + r4]
+ punpcklwd xm2, xm3
+ lea r0, [r0 + 4 * r1]
+ movq xm4, [r0]
+ punpcklwd xm3, xm4
+ vinserti128 m2, m2, xm3, 1 ; m2 = [4 3 3 2]
+ pmaddwd m5, m2, [r5 + 1 * mmsize]
+ pmaddwd m2, [r5]
+ paddd m0, m5
+ movq xm3, [r0 + r1]
+ punpcklwd xm4, xm3
+ movq xm1, [r0 + r1 * 2]
+ punpcklwd xm3, xm1
+ vinserti128 m4, m4, xm3, 1 ; m4 = [6 5 5 4]
+ pmaddwd m5, m4, [r5 + 1 * mmsize]
+ paddd m2, m5
+ pmaddwd m4, [r5]
+ movq xm3, [r0 + r4]
+ punpcklwd xm1, xm3
+ lea r0, [r0 + 4 * r1]
+ movq xm6, [r0]
+ punpcklwd xm3, xm6
+ vinserti128 m1, m1, xm3, 1 ; m1 = [8 7 7 6]
+ pmaddwd m5, m1, [r5 + 1 * mmsize]
+ paddd m4, m5
+ pmaddwd m1, [r5]
+ movq xm3, [r0 + r1]
+ punpcklwd xm6, xm3
+ movq xm5, [r0 + 2 * r1]
+ punpcklwd xm3, xm5
+ vinserti128 m6, m6, xm3, 1 ; m6 = [A 9 9 8]
+ pmaddwd m6, [r5 + 1 * mmsize]
+ paddd m1, m6
+ lea r4, [r3 * 3]
+
+%ifidn %1,sp
+ paddd m0, m7
+ paddd m2, m7
+ paddd m4, m7
+ paddd m1, m7
+ psrad m0, 12
+ psrad m2, 12
+ psrad m4, 12
+ psrad m1, 12
+%else
+ psrad m0, 6
+ psrad m2, 6
+ psrad m4, 6
+ psrad m1, 6
+%endif
+ packssdw m0, m2
+ packssdw m4, m1
+%ifidn %1,sp
+ packuswb m0, m4
+ vextracti128 xm2, m0, 1
+ movd [r2], xm0
+ movd [r2 + r3], xm2
+ pextrd [r2 + r3 * 2], xm0, 1
+ pextrd [r2 + r4], xm2, 1
+ lea r2, [r2 + r3 * 4]
+ pextrd [r2], xm0, 2
+ pextrd [r2 + r3], xm2, 2
+ pextrd [r2 + r3 * 2], xm0, 3
+ pextrd [r2 + r4], xm2, 3
+%else
+ vextracti128 xm2, m0, 1
+ vextracti128 xm1, m4, 1
+ movq [r2], xm0
+ movq [r2 + r3], xm2
+ movhps [r2 + r3 * 2], xm0
+ movhps [r2 + r4], xm2
+ lea r2, [r2 + r3 * 4]
+ movq [r2], xm4
+ movq [r2 + r3], xm1
+ movhps [r2 + r3 * 2], xm4
+ movhps [r2 + r4], xm1
+%endif
+ RET
+%endmacro
+
+FILTER_VER_CHROMA_S_AVX2_4x8 sp
+FILTER_VER_CHROMA_S_AVX2_4x8 ss
+
%macro FILTER_VER_CHROMA_S_AVX2_8x8 1
INIT_YMM avx2
cglobal interp_4tap_vert_%1_8x8, 4, 6, 8
More information about the x265-devel
mailing list