[x265] [PATCH 3 of 4] asm: filter_vsp[4x2], filter_vss[4x2] in avx2: 237c->137c, 206c->118c

[Divya Manivannan]

# HG changeset patch
# User Divya Manivannan <divya at multicorewareinc.com>
# Date 1426481230 -19800
#      Mon Mar 16 10:17:10 2015 +0530
# Node ID 90e0a1ae833dfa0e01628b490eafa98bf138440b
# Parent  302eecb0472f235908c6b49353e4d85e52695a6f
asm: filter_vsp[4x2], filter_vss[4x2] in avx2: 237c->137c, 206c->118c

diff -r 302eecb0472f -r 90e0a1ae833d source/common/x86/asm-primitives.cpp
--- a/source/common/x86/asm-primitives.cpp	Mon Mar 16 10:14:19 2015 +0530
+++ b/source/common/x86/asm-primitives.cpp	Mon Mar 16 10:17:10 2015 +0530
@@ -1653,6 +1653,7 @@
         p.chroma[X265_CSP_I420].pu[CHROMA_420_8x8].filter_vsp = x265_interp_4tap_vert_sp_8x8_avx2;
         p.chroma[X265_CSP_I420].pu[CHROMA_420_16x16].filter_vsp = x265_interp_4tap_vert_sp_16x16_avx2;
         p.chroma[X265_CSP_I420].pu[CHROMA_420_32x32].filter_vsp = x265_interp_4tap_vert_sp_32x32_avx2;
+        p.chroma[X265_CSP_I420].pu[CHROMA_420_4x2].filter_vsp = x265_interp_4tap_vert_sp_4x2_avx2;
         p.chroma[X265_CSP_I420].pu[CHROMA_420_4x8].filter_vsp = x265_interp_4tap_vert_sp_4x8_avx2;
         p.chroma[X265_CSP_I420].pu[CHROMA_420_4x16].filter_vsp = x265_interp_4tap_vert_sp_4x16_avx2;
         p.chroma[X265_CSP_I420].pu[CHROMA_420_16x32].filter_vsp = x265_interp_4tap_vert_sp_16x32_avx2;
@@ -1663,6 +1664,7 @@
         p.chroma[X265_CSP_I420].pu[CHROMA_420_8x8].filter_vss = x265_interp_4tap_vert_ss_8x8_avx2;
         p.chroma[X265_CSP_I420].pu[CHROMA_420_16x16].filter_vss = x265_interp_4tap_vert_ss_16x16_avx2;
         p.chroma[X265_CSP_I420].pu[CHROMA_420_32x32].filter_vss = x265_interp_4tap_vert_ss_32x32_avx2;
+        p.chroma[X265_CSP_I420].pu[CHROMA_420_4x2].filter_vss = x265_interp_4tap_vert_ss_4x2_avx2;
         p.chroma[X265_CSP_I420].pu[CHROMA_420_4x8].filter_vss = x265_interp_4tap_vert_ss_4x8_avx2;
         p.chroma[X265_CSP_I420].pu[CHROMA_420_4x16].filter_vss = x265_interp_4tap_vert_ss_4x16_avx2;
         p.chroma[X265_CSP_I420].pu[CHROMA_420_16x32].filter_vss = x265_interp_4tap_vert_ss_16x32_avx2;
diff -r 302eecb0472f -r 90e0a1ae833d source/common/x86/ipfilter8.asm
--- a/source/common/x86/ipfilter8.asm	Mon Mar 16 10:14:19 2015 +0530
+++ b/source/common/x86/ipfilter8.asm	Mon Mar 16 10:17:10 2015 +0530
@@ -13095,6 +13095,63 @@
 FILTER_VER_CHROMA_S_AVX2_4x16 sp
 FILTER_VER_CHROMA_S_AVX2_4x16 ss
 
+%macro FILTER_VER_CHROMA_S_AVX2_4x2 1
+INIT_YMM avx2
+cglobal interp_4tap_vert_%1_4x2, 4, 6, 6
+    mov             r4d, r4m
+    shl             r4d, 6
+    add             r1d, r1d
+    sub             r0, r1
+
+%ifdef PIC
+    lea             r5, [pw_ChromaCoeffV]
+    add             r5, r4
+%else
+    lea             r5, [pw_ChromaCoeffV + r4]
+%endif
+
+    lea             r4, [r1 * 3]
+%ifidn %1,sp
+    mova            m5, [pd_526336]
+%else
+    add             r3d, r3d
+%endif
+    movq            xm0, [r0]
+    movq            xm1, [r0 + r1]
+    punpcklwd       xm0, xm1
+    movq            xm2, [r0 + r1 * 2]
+    punpcklwd       xm1, xm2
+    vinserti128     m0, m0, xm1, 1                  ; m0 = [2 1 1 0]
+    pmaddwd         m0, [r5]
+    movq            xm3, [r0 + r4]
+    punpcklwd       xm2, xm3
+    movq            xm4, [r0 + 4 * r1]
+    punpcklwd       xm3, xm4
+    vinserti128     m2, m2, xm3, 1                  ; m2 = [4 3 3 2]
+    pmaddwd         m2, [r5 + 1 * mmsize]
+    paddd           m0, m2
+%ifidn %1,sp
+    paddd           m0, m5
+    psrad           m0, 12
+%else
+    psrad           m0, 6
+%endif
+    vextracti128    xm1, m0, 1
+    packssdw        xm0, xm1
+%ifidn %1,sp
+    packuswb        xm0, xm0
+    movd            [r2], xm0
+    pextrd          [r2 + r3], xm0, 1
+%else
+    movq            [r2], xm0
+    movhps          [r2 + r3], xm0
+%endif
+    RET
+%endmacro
+
+FILTER_VER_CHROMA_S_AVX2_4x2 sp
+FILTER_VER_CHROMA_S_AVX2_4x2 ss
+
 %macro FILTER_VER_CHROMA_S_AVX2_8x8 1
 INIT_YMM avx2
 cglobal interp_4tap_vert_%1_8x8, 4, 6, 8