[x265] [PATCH 1 of 9] asm-intra_pred_ang16_30: improve ~39% on SSE4

praveen at multicorewareinc.com praveen at multicorewareinc.com
Tue Mar 17 06:11:02 CET 2015


# HG changeset patch
# User Praveen Tiwari <praveen at multicorewareinc.com>
# Date 1426511897 -19800
# Node ID e39adace19812ba39f96c0943290c26ed302e054
# Parent  b9948752d5516a72eeaf824e3ee6f0feb097381c
asm-intra_pred_ang16_30: improve ~39% on SSE4

AVX2:
intra_ang_16x16[30]     17.63x   466.03          8216.22

SSE4:
intra_ang_16x16[30]     10.46x   773.18          8087.02

diff -r b9948752d551 -r e39adace1981 source/common/x86/asm-primitives.cpp
--- a/source/common/x86/asm-primitives.cpp	Mon Mar 16 20:40:12 2015 -0500
+++ b/source/common/x86/asm-primitives.cpp	Mon Mar 16 18:48:17 2015 +0530
@@ -1512,6 +1512,7 @@
         p.cu[BLOCK_16x16].intra_pred[28] = x265_intra_pred_ang16_28_avx2;
         p.cu[BLOCK_16x16].intra_pred[27] = x265_intra_pred_ang16_27_avx2;
         p.cu[BLOCK_16x16].intra_pred[29] = x265_intra_pred_ang16_29_avx2;
+        p.cu[BLOCK_16x16].intra_pred[30] = x265_intra_pred_ang16_30_avx2;
 
         // copy_sp primitives
         p.cu[BLOCK_16x16].copy_sp = x265_blockcopy_sp_16x16_avx2;
diff -r b9948752d551 -r e39adace1981 source/common/x86/intrapred.h
--- a/source/common/x86/intrapred.h	Mon Mar 16 20:40:12 2015 -0500
+++ b/source/common/x86/intrapred.h	Mon Mar 16 18:48:17 2015 +0530
@@ -187,6 +187,7 @@
 void x265_intra_pred_ang16_28_avx2(pixel* dst, intptr_t dstStride, const pixel* srcPix, int dirMode, int bFilter);
 void x265_intra_pred_ang16_27_avx2(pixel* dst, intptr_t dstStride, const pixel* srcPix, int dirMode, int bFilter);
 void x265_intra_pred_ang16_29_avx2(pixel* dst, intptr_t dstStride, const pixel* srcPix, int dirMode, int bFilter);
+void x265_intra_pred_ang16_30_avx2(pixel* dst, intptr_t dstStride, const pixel* srcPix, int dirMode, int bFilter);
 void x265_all_angs_pred_4x4_sse4(pixel *dest, pixel *refPix, pixel *filtPix, int bLuma);
 void x265_all_angs_pred_8x8_sse4(pixel *dest, pixel *refPix, pixel *filtPix, int bLuma);
 void x265_all_angs_pred_16x16_sse4(pixel *dest, pixel *refPix, pixel *filtPix, int bLuma);
diff -r b9948752d551 -r e39adace1981 source/common/x86/intrapred8.asm
--- a/source/common/x86/intrapred8.asm	Mon Mar 16 20:40:12 2015 -0500
+++ b/source/common/x86/intrapred8.asm	Mon Mar 16 18:48:17 2015 +0530
@@ -162,6 +162,18 @@
                      db 11, 21, 11, 21, 11, 21, 11, 21, 11, 21, 11, 21, 11, 21, 11, 21, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30
                      db 25, 7, 25, 7, 25, 7, 25, 7, 25, 7, 25, 7, 25, 7, 25, 7, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16
 
+
+ALIGN 32
+c_ang16_mode_30:      db 19, 13, 19, 13, 19, 13, 19, 13, 19, 13, 19, 13, 19, 13, 19, 13, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26
+                      db 25, 7, 25, 7, 25, 7, 25, 7, 25, 7, 25, 7, 25, 7, 25, 7, 12, 20, 12, 20, 12, 20, 12, 20, 12, 20, 12, 20, 12, 20, 12, 20
+                      db 31, 1, 31, 1, 31, 1, 31, 1, 31, 1, 31, 1, 31, 1, 31, 1, 18, 14, 18, 14, 18, 14, 18, 14, 18, 14, 18, 14, 18, 14, 18, 14
+                      db 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27
+                      db 24, 8, 24, 8, 24, 8, 24, 8, 24, 8, 24, 8, 24, 8, 24, 8, 11, 21, 11, 21, 11, 21, 11, 21, 11, 21, 11, 21, 11, 21, 11, 21
+                      db 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 17, 15, 17, 15, 17, 15, 17, 15, 17, 15, 17, 15, 17, 15, 17, 15
+                      db 4, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28
+                      db 23, 9, 23, 9, 23, 9, 23, 9, 23, 9, 23, 9, 23, 9, 23, 9, 10, 22, 10, 22, 10, 22, 10, 22, 10, 22, 10, 22, 10, 22, 10, 22
+                      db 29, 3, 29, 3, 29, 3, 29, 3, 29, 3, 29, 3, 29, 3, 29, 3, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16
+
 ALIGN 32
 ;; (blkSize - 1 - x)
 pw_planar4_0:         dw 3,  2,  1,  0,  3,  2,  1,  0
@@ -10910,3 +10922,77 @@
 
     INTRA_PRED_ANG16_MC0 r0 + 2 * r1, r0 + r3, 0
     RET
+
+INIT_YMM avx2
+cglobal intra_pred_ang16_30, 3, 5, 6
+    mova              m0, [pw_1024]
+    mova              m5, [intra_pred_shuff_0_8]
+    lea               r3, [3 * r1]
+    lea               r4, [c_ang16_mode_30]
+
+    vbroadcasti128    m1, [r2 + 1]
+    pshufb            m1, m5
+    vbroadcasti128    m2, [r2 + 9]
+    pshufb            m2, m5
+
+    INTRA_PRED_ANG16_MC0 r0, r0 + r1, 0
+
+    vbroadcasti128    m1, [r2 + 2]
+    pshufb            m1, m5
+    vbroadcasti128    m2, [r2 + 10]
+    pshufb            m2, m5
+
+    INTRA_PRED_ANG16_MC0 r0 + 2 * r1, r0 + r3, 1
+
+    vbroadcasti128    m1, [r2 + 3]
+    pshufb            m1, m5
+    vbroadcasti128    m2, [r2 + 11]
+    pshufb            m2, m5
+
+    lea               r0, [r0 + 4 * r1]
+    INTRA_PRED_ANG16_MC0 r0, r0 + r1, 2
+
+    vperm2i128        m1, m1, m2, 00100000b
+    pmaddubsw         m3, m1, [r4 + 3 * mmsize]
+    pmulhrsw          m3, m0
+    packuswb          m3, m3
+    vpermq            m3, m3, 11011000b
+    movu              [r0 + 2 * r1], xm3
+
+    vbroadcasti128    m1, [r2 + 4]
+    pshufb            m1, m5
+    vbroadcasti128    m2, [r2 + 12]
+    pshufb            m2, m5
+
+    add               r4, 4 * mmsize
+    INTRA_PRED_ANG16_MC0 r0 + r3, r0 + 4 * r1, 0
+
+    vbroadcasti128    m1, [r2 + 5]
+    pshufb            m1, m5
+    vbroadcasti128    m2, [r2 + 13]
+    pshufb            m2, m5
+
+    lea               r0, [r0 + 4 * r1]
+    INTRA_PRED_ANG16_MC0 r0 + r1, r0 + 2 * r1, 1
+
+    vperm2i128        m1, m1, m2, 00100000b
+    pmaddubsw         m3, m1, [r4 + 2 * mmsize]
+    pmulhrsw          m3, m0
+    packuswb          m3, m3
+    vpermq            m3, m3, 11011000b
+    movu              [r0 + r3], xm3
+
+    vbroadcasti128    m1, [r2 + 6]
+    pshufb            m1, m5
+    vbroadcasti128    m2, [r2 + 14]
+    pshufb            m2, m5
+
+    lea               r0, [r0 + 4 * r1]
+    INTRA_PRED_ANG16_MC0 r0, r0 + r1, 3
+
+    vbroadcasti128    m1, [r2 + 7]
+    pshufb            m1, m5
+    vbroadcasti128    m2, [r2 + 15]
+    pshufb            m2, m5
+    INTRA_PRED_ANG16_MC0 r0 + 2 * r1, r0 + r3, 4
+    RET


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