[x265] [PATCH 2 of 4] asm-intra_pred_ang16_23: improve speedup by ~22% over SSE4

[praveen at multicorewareinc.com]

# HG changeset patch
# User Praveen Tiwari <praveen at multicorewareinc.com>
# Date 1426589578 -19800
# Node ID 8e96973847fdcb5140a67ae3a67e66dfb87b5040
# Parent  109d1caf0fe85359ce096e00bf841928800139ec
asm-intra_pred_ang16_23: improve speedup by ~22% over SSE4

AVX2:
intra_ang_16x16[23]     16.53x   502.81           8312.49

SSE4:
intra_ang_16x16[23]     13.41x   645.65           8658.00

diff -r 109d1caf0fe8 -r 8e96973847fd source/common/x86/asm-primitives.cpp
--- a/source/common/x86/asm-primitives.cpp	Tue Mar 17 13:06:03 2015 +0530
+++ b/source/common/x86/asm-primitives.cpp	Tue Mar 17 16:22:58 2015 +0530
@@ -1528,6 +1528,7 @@
         p.cu[BLOCK_16x16].intra_pred[32] = x265_intra_pred_ang16_32_avx2;
         p.cu[BLOCK_16x16].intra_pred[33] = x265_intra_pred_ang16_33_avx2;
         p.cu[BLOCK_16x16].intra_pred[24] = x265_intra_pred_ang16_24_avx2;
+        p.cu[BLOCK_16x16].intra_pred[23] = x265_intra_pred_ang16_23_avx2;
 
         // copy_sp primitives
         p.cu[BLOCK_16x16].copy_sp = x265_blockcopy_sp_16x16_avx2;
diff -r 109d1caf0fe8 -r 8e96973847fd source/common/x86/intrapred.h
--- a/source/common/x86/intrapred.h	Tue Mar 17 13:06:03 2015 +0530
+++ b/source/common/x86/intrapred.h	Tue Mar 17 16:22:58 2015 +0530
@@ -192,6 +192,7 @@
 void x265_intra_pred_ang16_32_avx2(pixel* dst, intptr_t dstStride, const pixel* srcPix, int dirMode, int bFilter);
 void x265_intra_pred_ang16_33_avx2(pixel* dst, intptr_t dstStride, const pixel* srcPix, int dirMode, int bFilter);
 void x265_intra_pred_ang16_24_avx2(pixel* dst, intptr_t dstStride, const pixel* srcPix, int dirMode, int bFilter);
+void x265_intra_pred_ang16_23_avx2(pixel* dst, intptr_t dstStride, const pixel* srcPix, int dirMode, int bFilter);
 void x265_all_angs_pred_4x4_sse4(pixel *dest, pixel *refPix, pixel *filtPix, int bLuma);
 void x265_all_angs_pred_8x8_sse4(pixel *dest, pixel *refPix, pixel *filtPix, int bLuma);
 void x265_all_angs_pred_16x16_sse4(pixel *dest, pixel *refPix, pixel *filtPix, int bLuma);
diff -r 109d1caf0fe8 -r 8e96973847fd source/common/x86/intrapred8.asm
--- a/source/common/x86/intrapred8.asm	Tue Mar 17 13:06:03 2015 +0530
+++ b/source/common/x86/intrapred8.asm	Tue Mar 17 16:22:58 2015 +0530
@@ -225,6 +225,17 @@
                      db 1, 31, 1, 31, 1, 31, 1, 31, 1, 31, 1, 31, 1, 31, 1, 31, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26
                      db 11, 21, 11, 21, 11, 21, 11, 21, 11, 21, 11, 21, 11, 21, 11, 21, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16
 
+ALIGN 32
+c_ang16_mode_23:     db 9, 23, 9, 23, 9, 23, 9, 23, 9, 23, 9, 23, 9, 23, 9, 23, 18, 14, 18, 14, 18, 14, 18, 14, 18, 14, 18, 14, 18, 14, 18, 14
+                     db 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5
+                     db 4, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28, 13, 19, 13, 19, 13, 19, 13, 19, 13, 19, 13, 19, 13, 19, 13, 19
+                     db 22, 10, 22, 10, 22, 10, 22, 10, 22, 10, 22, 10, 22, 10, 22, 10, 31, 1, 31, 1, 31, 1, 31, 1, 31, 1, 31, 1, 31, 1, 31, 1
+                     db 8, 24, 8, 24, 8, 24, 8, 24, 8, 24, 8, 24, 8, 24, 8, 24, 17, 15, 17, 15, 17, 15, 17, 15, 17, 15, 17, 15, 17, 15, 17, 15
+                     db 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6
+                     db 3, 29, 3, 29, 3, 29, 3, 29, 3, 29, 3, 29, 3, 29, 3, 29, 12, 20, 12, 20, 12, 20, 12, 20, 12, 20, 12, 20, 12, 20, 12, 20
+                     db 21, 11, 21, 11, 21, 11, 21, 11, 21, 11, 21, 11, 21, 11, 21, 11, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2
+                     db 7, 25, 7, 25, 7, 25, 7, 25, 7, 25, 7, 25, 7, 25, 7, 25, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16
+
 ALIGN 32
 ;; (blkSize - 1 - x)
 pw_planar4_0:         dw 3,  2,  1,  0,  3,  2,  1,  0
@@ -11183,3 +11194,59 @@
 
     INTRA_PRED_ANG16_MC1 2
     RET
+
+INIT_YMM avx2
+cglobal intra_pred_ang16_23, 3, 5, 7
+    mova              m0, [pw_1024]
+    mova              m5, [intra_pred_shuff_0_8]
+    lea               r3, [3 * r1]
+    lea               r4, [c_ang16_mode_23]
+
+    INTRA_PRED_ANG16_MC2 0
+    INTRA_PRED_ANG16_MC0 r0, r0 + r1, 0
+    INTRA_PRED_ANG16_MC3 r0 + 2 * r1, 1
+
+    movu              xm6, [r2 - 1]
+    pinsrb            xm6, [r2 + 36], 0
+    vinserti128       m1, m6, xm6, 1
+    pshufb            m1, m5
+    vbroadcasti128    m2, [r2 + 7]
+    pshufb            m2, m5
+    INTRA_PRED_ANG16_MC0 r0 + r3, r0 + 4 * r1, 2
+
+    lea                  r0, [r0 + 4 * r1]
+
+    INTRA_PRED_ANG16_MC0 r0 + r1, r0 + 2 * r1, 3
+
+    add               r4, 4 * mmsize
+
+    pslldq            xm6,  xm6, 1
+    pinsrb            xm6, [r2 + 39], 0
+    vinserti128       m1, m6, xm6, 1
+    pshufb            m1, m5
+    vbroadcasti128    m2, [r2 + 6]
+    pshufb            m2, m5
+    INTRA_PRED_ANG16_MC0 r0 + r3, r0 + 4 * r1, 0
+
+    lea                  r0, [r0 + 4 * r1]
+    INTRA_PRED_ANG16_MC3 r0 + r1, 1
+
+    pslldq            xm6, xm6, 1
+    pinsrb            xm6, [r2 + 43], 0
+    vinserti128       m1, m6, xm6, 1
+    pshufb            m1, m5
+    vbroadcasti128    m2, [r2 + 5]
+    pshufb            m2, m5
+    INTRA_PRED_ANG16_MC0 r0 + 2 * r1, r0 + r3, 2
+    lea                  r0, [r0 + 4 * r1]
+    INTRA_PRED_ANG16_MC0 r0, r0 + r1, 3
+
+    add               r4, 4 * mmsize
+    pslldq            xm6,  xm6, 1
+    pinsrb            xm6, [r2 + 46], 0
+    vinserti128       m1, m6, xm6, 1
+    pshufb            m1, m5
+    vbroadcasti128    m2, [r2 + 4]
+    pshufb            m2, m5
+    INTRA_PRED_ANG16_MC0 r0 + 2 * r1, r0 + r3, 0
+    RET