[x265] [PATCH 2 of 4] asm-intra_pred_ang32_27: use macro to reduce code size
praveen at multicorewareinc.com
praveen at multicorewareinc.com
Tue Mar 24 06:01:29 CET 2015
# HG changeset patch
# User Praveen Tiwari <praveen at multicorewareinc.com>
# Date 1427114016 -19800
# Mon Mar 23 18:03:36 2015 +0530
# Node ID 0f6f993ccfc3fe13b4b5272dfabcca7480a0ca2f
# Parent ef5801c1396884bf96c5abc09d6664cd31e213d0
asm-intra_pred_ang32_27: use macro to reduce code size
diff -r ef5801c13968 -r 0f6f993ccfc3 source/common/x86/intrapred8.asm
--- a/source/common/x86/intrapred8.asm Mon Mar 23 17:59:36 2015 +0530
+++ b/source/common/x86/intrapred8.asm Mon Mar 23 18:03:36 2015 +0530
@@ -11427,24 +11427,7 @@
INTRA_PRED_ANG32_STORE
RET
-INIT_YMM avx2
-cglobal intra_pred_ang32_27, 3, 5, 11
- mova m0, [pw_1024]
- mova m1, [intra_pred_shuff_0_8]
- lea r3, [3 * r1]
- lea r4, [c_ang32_mode_27]
-
- vbroadcasti128 m2, [r2 + 1]
- pshufb m2, m1
- vbroadcasti128 m3, [r2 + 9]
- pshufb m3, m1
- vbroadcasti128 m4, [r2 + 17]
- pshufb m4, m1
- vbroadcasti128 m5, [r2 + 25]
- pshufb m5, m1
-
- ;row [0, 1]
- mova m10, [r4 + 0 * mmsize]
+%macro INTRA_PRED_ANG32_CAL_ROW 0
pmaddubsw m6, m2, m10
pmulhrsw m6, m0
pmaddubsw m7, m3, m10
@@ -11457,58 +11440,50 @@
packuswb m8, m9
vperm2i128 m7, m6, m8, 00100000b
vperm2i128 m6, m6, m8, 00110001b
+%endmacro
+
+INIT_YMM avx2
+cglobal intra_pred_ang32_27, 3, 5, 11
+ mova m0, [pw_1024]
+ mova m1, [intra_pred_shuff_0_8]
+ lea r3, [3 * r1]
+ lea r4, [c_ang32_mode_27]
+
+ vbroadcasti128 m2, [r2 + 1]
+ pshufb m2, m1
+ vbroadcasti128 m3, [r2 + 9]
+ pshufb m3, m1
+ vbroadcasti128 m4, [r2 + 17]
+ pshufb m4, m1
+ vbroadcasti128 m5, [r2 + 25]
+ pshufb m5, m1
+
+ ;row [0, 1]
+ mova m10, [r4 + 0 * mmsize]
+
+ INTRA_PRED_ANG32_CAL_ROW
movu [r0], m7
movu [r0 + r1], m6
;row [2, 3]
mova m10, [r4 + 1 * mmsize]
- pmaddubsw m6, m2, m10
- pmulhrsw m6, m0
- pmaddubsw m7, m3, m10
- pmulhrsw m7, m0
- pmaddubsw m8, m4, m10
- pmulhrsw m8, m0
- pmaddubsw m9, m5, m10
- pmulhrsw m9, m0
- packuswb m6, m7
- packuswb m8, m9
- vperm2i128 m7, m6, m8, 00100000b
- vperm2i128 m6, m6, m8, 00110001b
+
+ INTRA_PRED_ANG32_CAL_ROW
movu [r0 + 2 * r1], m7
movu [r0 + r3], m6
;row [4, 5]
mova m10, [r4 + 2 * mmsize]
lea r0, [r0 + 4 * r1]
- pmaddubsw m6, m2, m10
- pmulhrsw m6, m0
- pmaddubsw m7, m3, m10
- pmulhrsw m7, m0
- pmaddubsw m8, m4, m10
- pmulhrsw m8, m0
- pmaddubsw m9, m5, m10
- pmulhrsw m9, m0
- packuswb m6, m7
- packuswb m8, m9
- vperm2i128 m7, m6, m8, 00100000b
- vperm2i128 m6, m6, m8, 00110001b
+
+ INTRA_PRED_ANG32_CAL_ROW
movu [r0], m7
movu [r0 + r1], m6
;row [6, 7]
mova m10, [r4 + 3 * mmsize]
- pmaddubsw m6, m2, m10
- pmulhrsw m6, m0
- pmaddubsw m7, m3, m10
- pmulhrsw m7, m0
- pmaddubsw m8, m4, m10
- pmulhrsw m8, m0
- pmaddubsw m9, m5, m10
- pmulhrsw m9, m0
- packuswb m6, m7
- packuswb m8, m9
- vperm2i128 m7, m6, m8, 00100000b
- vperm2i128 m6, m6, m8, 00110001b
+
+ INTRA_PRED_ANG32_CAL_ROW
movu [r0 + 2 * r1], m7
movu [r0 + r3], m6
@@ -11516,53 +11491,23 @@
lea r0, [r0 + 4 * r1]
add r4, 4 * mmsize
mova m10, [r4 + 0 * mmsize]
- pmaddubsw m6, m2, m10
- pmulhrsw m6, m0
- pmaddubsw m7, m3, m10
- pmulhrsw m7, m0
- pmaddubsw m8, m4, m10
- pmulhrsw m8, m0
- pmaddubsw m9, m5, m10
- pmulhrsw m9, m0
- packuswb m6, m7
- packuswb m8, m9
- vperm2i128 m7, m6, m8, 00100000b
- vperm2i128 m6, m6, m8, 00110001b
+
+ INTRA_PRED_ANG32_CAL_ROW
movu [r0], m7
movu [r0 + r1], m6
;row [10, 11]
mova m10, [r4 + 1 * mmsize]
- pmaddubsw m6, m2, m10
- pmulhrsw m6, m0
- pmaddubsw m7, m3, m10
- pmulhrsw m7, m0
- pmaddubsw m8, m4, m10
- pmulhrsw m8, m0
- pmaddubsw m9, m5, m10
- pmulhrsw m9, m0
- packuswb m6, m7
- packuswb m8, m9
- vperm2i128 m7, m6, m8, 00100000b
- vperm2i128 m6, m6, m8, 00110001b
+
+ INTRA_PRED_ANG32_CAL_ROW
movu [r0 + 2 * r1], m7
movu [r0 + r3], m6
;row [12, 13]
lea r0, [r0 + 4 * r1]
mova m10, [r4 + 2 * mmsize]
- pmaddubsw m6, m2, m10
- pmulhrsw m6, m0
- pmaddubsw m7, m3, m10
- pmulhrsw m7, m0
- pmaddubsw m8, m4, m10
- pmulhrsw m8, m0
- pmaddubsw m9, m5, m10
- pmulhrsw m9, m0
- packuswb m6, m7
- packuswb m8, m9
- vperm2i128 m7, m6, m8, 00100000b
- vperm2i128 m6, m6, m8, 00110001b
+
+ INTRA_PRED_ANG32_CAL_ROW
movu [r0], m7
movu [r0 + r1], m6
@@ -11590,142 +11535,62 @@
;row [15, 16]
add r4, 4 * mmsize
mova m10, [r4 + 0 * mmsize]
- pmaddubsw m6, m2, m10
- pmulhrsw m6, m0
- pmaddubsw m7, m3, m10
- pmulhrsw m7, m0
- pmaddubsw m8, m4, m10
- pmulhrsw m8, m0
- pmaddubsw m9, m5, m10
- pmulhrsw m9, m0
- packuswb m6, m7
- packuswb m8, m9
- vperm2i128 m7, m6, m8, 00100000b
- vperm2i128 m6, m6, m8, 00110001b
+
+ INTRA_PRED_ANG32_CAL_ROW
movu [r0 + r3], m7
lea r0, [r0 + 4 * r1]
movu [r0], m6
;row [17, 18]
mova m10, [r4 + 1 * mmsize]
- pmaddubsw m6, m2, m10
- pmulhrsw m6, m0
- pmaddubsw m7, m3, m10
- pmulhrsw m7, m0
- pmaddubsw m8, m4, m10
- pmulhrsw m8, m0
- pmaddubsw m9, m5, m10
- pmulhrsw m9, m0
- packuswb m6, m7
- packuswb m8, m9
- vperm2i128 m7, m6, m8, 00100000b
- vperm2i128 m6, m6, m8, 00110001b
+
+ INTRA_PRED_ANG32_CAL_ROW
movu [r0 + r1], m7
movu [r0 + 2 * r1], m6
;row [19, 20]
mova m10, [r4 + 2 * mmsize]
- pmaddubsw m6, m2, m10
- pmulhrsw m6, m0
- pmaddubsw m7, m3, m10
- pmulhrsw m7, m0
- pmaddubsw m8, m4, m10
- pmulhrsw m8, m0
- pmaddubsw m9, m5, m10
- pmulhrsw m9, m0
- packuswb m6, m7
- packuswb m8, m9
- vperm2i128 m7, m6, m8, 00100000b
- vperm2i128 m6, m6, m8, 00110001b
+
+ INTRA_PRED_ANG32_CAL_ROW
movu [r0 + r3], m7
lea r0, [r0 + 4 * r1]
movu [r0], m6
;row [21, 22]
mova m10, [r4 + 3 * mmsize]
- pmaddubsw m6, m2, m10
- pmulhrsw m6, m0
- pmaddubsw m7, m3, m10
- pmulhrsw m7, m0
- pmaddubsw m8, m4, m10
- pmulhrsw m8, m0
- pmaddubsw m9, m5, m10
- pmulhrsw m9, m0
- packuswb m6, m7
- packuswb m8, m9
- vperm2i128 m7, m6, m8, 00100000b
- vperm2i128 m6, m6, m8, 00110001b
+
+ INTRA_PRED_ANG32_CAL_ROW
movu [r0 + r1], m7
movu [r0 + 2 * r1], m6
;row [23, 24]
add r4, 4 * mmsize
mova m10, [r4 + 0 * mmsize]
- pmaddubsw m6, m2, m10
- pmulhrsw m6, m0
- pmaddubsw m7, m3, m10
- pmulhrsw m7, m0
- pmaddubsw m8, m4, m10
- pmulhrsw m8, m0
- pmaddubsw m9, m5, m10
- pmulhrsw m9, m0
- packuswb m6, m7
- packuswb m8, m9
- vperm2i128 m7, m6, m8, 00100000b
- vperm2i128 m6, m6, m8, 00110001b
+
+ INTRA_PRED_ANG32_CAL_ROW
movu [r0 + r3], m7
lea r0, [r0 + 4 * r1]
movu [r0], m6
;row [25, 26]
mova m10, [r4 + 1 * mmsize]
- pmaddubsw m6, m2, m10
- pmulhrsw m6, m0
- pmaddubsw m7, m3, m10
- pmulhrsw m7, m0
- pmaddubsw m8, m4, m10
- pmulhrsw m8, m0
- pmaddubsw m9, m5, m10
- pmulhrsw m9, m0
- packuswb m6, m7
- packuswb m8, m9
- vperm2i128 m7, m6, m8, 00100000b
- vperm2i128 m6, m6, m8, 00110001b
+
+ INTRA_PRED_ANG32_CAL_ROW
movu [r0 + r1], m7
movu [r0 + 2 * r1], m6
;row [27, 28]
mova m10, [r4 + 2 * mmsize]
- pmaddubsw m6, m2, m10
- pmulhrsw m6, m0
- pmaddubsw m7, m3, m10
- pmulhrsw m7, m0
- pmaddubsw m8, m4, m10
- pmulhrsw m8, m0
- pmaddubsw m9, m5, m10
- pmulhrsw m9, m0
- packuswb m6, m7
- packuswb m8, m9
- vperm2i128 m7, m6, m8, 00100000b
- vperm2i128 m6, m6, m8, 00110001b
+
+ INTRA_PRED_ANG32_CAL_ROW
movu [r0 + r3], m7
lea r0, [r0 + 4 * r1]
movu [r0], m6
;row [29, 30]
mova m10, [r4 + 3 * mmsize]
- pmaddubsw m6, m2, m10
- pmulhrsw m6, m0
- pmaddubsw m7, m3, m10
- pmulhrsw m7, m0
- pmaddubsw m8, m4, m10
- pmulhrsw m8, m0
- pmaddubsw m9, m5, m10
- pmulhrsw m9, m0
- packuswb m6, m7
- packuswb m8, m9
- vperm2i128 m7, m6, m8, 00100000b
- vperm2i128 m6, m6, m8, 00110001b
+
+ INTRA_PRED_ANG32_CAL_ROW
movu [r0 + r1], m7
movu [r0 + 2 * r1], m6
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