[x265] [PATCH] asm: chroma_hps[2x4] avx2 - improved 348c->274c

aasaipriya at multicorewareinc.com aasaipriya at multicorewareinc.com
Wed Mar 25 05:21:02 CET 2015


# HG changeset patch
# User Aasaipriya Chandran <aasaipriya at multicorewareinc.com>
# Date 1427257237 -19800
#      Wed Mar 25 09:50:37 2015 +0530
# Node ID ba00598f3ad32867e9a12898ace89e3210b75061
# Parent  489c40ea0b7b568e5815b9aecfa60c286cd8bfbc
asm: chroma_hps[2x4] avx2 - improved 348c->274c

diff -r 489c40ea0b7b -r ba00598f3ad3 source/common/x86/asm-primitives.cpp
--- a/source/common/x86/asm-primitives.cpp	Wed Mar 25 09:42:42 2015 +0530
+++ b/source/common/x86/asm-primitives.cpp	Wed Mar 25 09:50:37 2015 +0530
@@ -1737,6 +1737,7 @@
         p.chroma[X265_CSP_I420].pu[CHROMA_420_32x16].filter_hps = x265_interp_4tap_horiz_ps_32x16_avx2;
         p.chroma[X265_CSP_I420].pu[CHROMA_420_32x24].filter_hps = x265_interp_4tap_horiz_ps_32x24_avx2;
         p.chroma[X265_CSP_I420].pu[CHROMA_420_32x8].filter_hps = x265_interp_4tap_horiz_ps_32x8_avx2;
+        p.chroma[X265_CSP_I420].pu[CHROMA_420_2x4].filter_hps = x265_interp_4tap_horiz_ps_2x4_avx2;
 
         p.chroma[X265_CSP_I422].pu[CHROMA_422_4x4].filter_vpp = x265_interp_4tap_vert_pp_4x4_avx2;
 
diff -r 489c40ea0b7b -r ba00598f3ad3 source/common/x86/ipfilter8.asm
--- a/source/common/x86/ipfilter8.asm	Wed Mar 25 09:42:42 2015 +0530
+++ b/source/common/x86/ipfilter8.asm	Wed Mar 25 09:50:37 2015 +0530
@@ -291,6 +291,9 @@
 ALIGN 32
 interp8_hps_shuf: dd 0, 4, 1, 5, 2, 6, 3, 7
 
+ALIGN 32
+interp4_hps_shuf: times 2 db 0, 1, 2, 3, 1, 2, 3, 4, 8, 9, 10, 11, 9, 10, 11, 12
+
 SECTION .text
 
 cextern pb_128
@@ -20223,3 +20226,64 @@
     IPFILTER_CHROMA_PS_8xN_AVX2  16
     IPFILTER_CHROMA_PS_8xN_AVX2  6
     IPFILTER_CHROMA_PS_8xN_AVX2  4
+
+INIT_YMM avx2
+cglobal interp_4tap_horiz_ps_2x4, 4, 7, 3
+    mov                r4d,            r4m
+    mov                r5d,            r5m
+    add                r3d,            r3d
+%ifdef PIC
+    lea                r6,             [tab_ChromaCoeff]
+    vpbroadcastd       m0,             [r6 + r4 * 4]
+%else
+    vpbroadcastd       m0,             [tab_ChromaCoeff + r4 * 4]
+%endif
+
+    mova               xm3,            [pw_2000]
+    dec                r0
+    test               r5d,            r5d
+    jz                 .label
+    sub                r0,             r1
+
+.label
+    lea                r6,             [r1 * 3]
+    movq               xm1,            [r0]
+    movhps             xm1,            [r0 + r1]
+    movq               xm2,            [r0 + r1 * 2]
+    movhps             xm2,            [r0 + r6]
+
+    vinserti128        m1,             m1,          xm2,          1
+    pshufb             m1,             [interp4_hps_shuf]
+    pmaddubsw          m1,             m0
+    pmaddwd            m1,             [pw_1]
+    vextracti128       xm2,            m1,          1
+    packssdw           xm1,            xm2
+    psubw              xm1,            xm3
+
+    lea                r4,             [r3 * 3]
+    movd               [r2],           xm1
+    pextrd             [r2 + r3],      xm1,         1
+    pextrd             [r2 + r3 * 2],  xm1,         2
+    pextrd             [r2 + r4],      xm1,         3
+
+    test               r5d,            r5d
+    jz                .end
+    lea                r2,             [r2 + r3 * 4]
+    lea                r0,             [r0 + r1 * 4]
+
+    movq               xm1,            [r0]
+    movhps             xm1,            [r0 + r1]
+    movq               xm2,            [r0 + r1 * 2]
+    vinserti128        m1,             m1,          xm2,          1
+    pshufb             m1,             [interp4_hps_shuf]
+    pmaddubsw          m1,             m0
+    pmaddwd            m1,             [pw_1]
+    vextracti128       xm2,            m1,          1
+    packssdw           xm1,            xm2
+    psubw              xm1,            xm3
+
+    movd               [r2],           xm1
+    pextrd             [r2 + r3],      xm1,         1
+    pextrd             [r2 + r3 * 2],  xm1,         2
+.end
+    RET


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