[x265] [PATCH] asm:intra_pred_ang4_2 improved by ~4% 134.99 -> 129.95 with nits and tweaks

[dave]

On 03/30/2015 11:49 AM, Steve Borho wrote:
> On 03/28, dtyx265 at gmail.com wrote:
>> # HG changeset patch
>> # User David T Yuen <dtyx265 at gmail.com>
>> # Date 1427590314 25200
>> # Node ID ea65ec5a6c969e4cee612faa4d948e3337ed72d1
>> # Parent  36d70728acc2d9d6103af7530493176c08298ded
>> asm:intra_pred_ang4_2 improved by ~4% 134.99 -> 129.95 with nits and tweaks
>>
>> Corrected parameter count
>> Reduced xmm registers to 1
> I have this one and two others flagged, but waiting for Min to finish
> reviewing the rest before queueing them.
>
> Min is travelling to India and will be off-line for about a day.
Thanks for letting me know.  Soon after all of the intra_ang4 patches 
have been accepted I will be submitting all of the high-bit versions.  I 
already have them working so I am just reviewing and refining my work.
>
>> diff -r 36d70728acc2 -r ea65ec5a6c96 source/common/x86/intrapred8.asm
>> --- a/source/common/x86/intrapred8.asm	Fri Mar 27 13:16:28 2015 -0500
>> +++ b/source/common/x86/intrapred8.asm	Sat Mar 28 17:51:54 2015 -0700
>> @@ -1320,7 +1320,7 @@
>>   ; void intraPredAng4(pixel* dst, intptr_t dstStride, pixel* src, int dirMode, int bFilter)
>>   ;-----------------------------------------------------------------------------------------
>>   INIT_XMM sse2
>> -cglobal intra_pred_ang4_2, 3,5,3
>> +cglobal intra_pred_ang4_2, 4,5,1
>>       lea         r4, [r2 + 2]
>>       add         r2, 10
>>       cmp         r3m, byte 34
>> @@ -1328,14 +1328,12 @@
>>   
>>       movh        m0, [r2]
>>       movd        [r0], m0
>> -    mova        m1, m0
>> -    psrldq      m1, 1
>> -    movd        [r0 + r1], m1
>> -    mova        m2, m0
>> -    psrldq      m2, 2
>> -    movd        [r0 + r1 * 2], m2
>> +    psrldq      m0, 1
>> +    movd        [r0 + r1], m0
>> +    psrldq      m0, 1
>> +    movd        [r0 + r1 * 2], m0
>>       lea         r1, [r1 * 3]
>> -    psrldq      m0, 3
>> +    psrldq      m0, 1
>>       movd        [r0 + r1], m0
>>       RET
>>   
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