[x265] [PATCH 3 of 3] asm: interp_4tap_vert_pp sse2

dtyx265 at gmail.com dtyx265 at gmail.com
Wed May 6 21:45:37 CEST 2015


# HG changeset patch
# User David T Yuen <dtyx265 at gmail.com>
# Date 1430941437 25200
# Node ID e08bcc7339b0c611728dd0245028f1b0c72c8bee
# Parent  ae9d689acc97b9165acfee5c32b257cc3823492f
asm: interp_4tap_vert_pp sse2

This replaces c code for 4x4, 4x8, 4x16 and 4x32

64-bit

./test/TestBench --testbench interp | grep vpp | grep " 4x"
chroma_vpp[  4x4]	2.08x 	 1012.50  	 2109.96
chroma_vpp[  4x2]	2.12x 	 527.48   	 1117.44
chroma_vpp[  4x8]	2.23x 	 1971.84  	 4400.13
chroma_vpp[ 4x16]	2.28x 	 3802.50  	 8675.20
chroma_vpp[  4x8]	2.25x 	 1952.50  	 4400.15
chroma_vpp[  4x4]	2.08x 	 1012.50  	 2109.94
chroma_vpp[ 4x16]	2.30x 	 3770.00  	 8675.10
chroma_vpp[ 4x32]	2.28x 	 7470.00  	 16995.07
chroma_vpp[  4x4]	2.08x 	 1012.50  	 2109.97
chroma_vpp[  4x8]	2.29x 	 1920.00  	 4400.14
chroma_vpp[ 4x16]	2.30x 	 3770.00  	 8675.11

32-bit

./test/TestBench --testbench interp | grep vpp | grep " 4x"
chroma_vpp[  4x4]	2.46x 	 1097.49  	 2697.42
chroma_vpp[  4x2]	2.30x 	 602.49   	 1387.41
chroma_vpp[  4x8]	2.81x 	 2012.50  	 5662.44
chroma_vpp[ 4x16]	2.86x 	 3887.50  	 11117.53
chroma_vpp[  4x8]	2.81x 	 2012.50  	 5662.44
chroma_vpp[  4x4]	2.46x 	 1095.00  	 2697.49
chroma_vpp[ 4x16]	2.86x 	 3887.50  	 11117.53
chroma_vpp[ 4x32]	2.88x 	 7574.29  	 21837.53
chroma_vpp[  4x4]	2.46x 	 1097.50  	 2697.33
chroma_vpp[  4x8]	2.81x 	 2012.50  	 5662.44
chroma_vpp[ 4x16]	2.86x 	 3887.50  	 11117.53

diff -r ae9d689acc97 -r e08bcc7339b0 source/common/x86/asm-primitives.cpp
--- a/source/common/x86/asm-primitives.cpp	Wed May 06 12:34:58 2015 -0700
+++ b/source/common/x86/asm-primitives.cpp	Wed May 06 12:43:57 2015 -0700
@@ -1359,8 +1359,18 @@
         p.chroma[X265_CSP_I420].pu[CHROMA_420_2x4].filter_vpp = x265_interp_4tap_vert_pp_2x4_sse2;
         p.chroma[X265_CSP_I420].pu[CHROMA_420_2x8].filter_vpp = x265_interp_4tap_vert_pp_2x8_sse2;
         p.chroma[X265_CSP_I420].pu[CHROMA_420_4x2].filter_vpp = x265_interp_4tap_vert_pp_4x2_sse2;
+        p.chroma[X265_CSP_I420].pu[CHROMA_420_4x4].filter_vpp = x265_interp_4tap_vert_pp_4x4_sse2;
+        p.chroma[X265_CSP_I420].pu[CHROMA_420_4x8].filter_vpp = x265_interp_4tap_vert_pp_4x8_sse2;
+        p.chroma[X265_CSP_I420].pu[CHROMA_420_4x16].filter_vpp = x265_interp_4tap_vert_pp_4x16_sse2;
         p.chroma[X265_CSP_I422].pu[CHROMA_422_2x8].filter_vpp = x265_interp_4tap_vert_pp_2x8_sse2;
         p.chroma[X265_CSP_I422].pu[CHROMA_422_2x16].filter_vpp = x265_interp_4tap_vert_pp_2x16_sse2;
+        p.chroma[X265_CSP_I422].pu[CHROMA_422_4x4].filter_vpp = x265_interp_4tap_vert_pp_4x4_sse2;
+        p.chroma[X265_CSP_I422].pu[CHROMA_422_4x8].filter_vpp = x265_interp_4tap_vert_pp_4x8_sse2;
+        p.chroma[X265_CSP_I422].pu[CHROMA_422_4x16].filter_vpp = x265_interp_4tap_vert_pp_4x16_sse2;
+        p.chroma[X265_CSP_I422].pu[CHROMA_422_4x32].filter_vpp = x265_interp_4tap_vert_pp_4x32_sse2;
+        p.chroma[X265_CSP_I444].pu[LUMA_4x4].filter_vpp = x265_interp_4tap_vert_pp_4x4_sse2;
+        p.chroma[X265_CSP_I444].pu[LUMA_4x8].filter_vpp = x265_interp_4tap_vert_pp_4x8_sse2;
+        p.chroma[X265_CSP_I444].pu[LUMA_4x16].filter_vpp = x265_interp_4tap_vert_pp_4x16_sse2;
 
         //p.frameInitLowres = x265_frame_init_lowres_core_mmx2;
         p.frameInitLowres = x265_frame_init_lowres_core_sse2;
diff -r ae9d689acc97 -r e08bcc7339b0 source/common/x86/ipfilter8.asm
--- a/source/common/x86/ipfilter8.asm	Wed May 06 12:34:58 2015 -0700
+++ b/source/common/x86/ipfilter8.asm	Wed May 06 12:43:57 2015 -0700
@@ -1244,6 +1244,142 @@
     RET
 
 ;-----------------------------------------------------------------------------
+; void interp_4tap_vert_pp_%1x%2(pixel *src, intptr_t srcStride, pixel *dst, intptr_t dstStride, int coeffIdx)
+;-----------------------------------------------------------------------------
+%macro FILTER_V4_W4_H4_sse2 1
+INIT_XMM sse2
+%if ARCH_X86_64
+cglobal interp_4tap_vert_pp_4x%1, 4, 6, 9
+%define PB_0 m8
+    pxor        m8,        m8
+%else
+cglobal interp_4tap_vert_pp_4x%1, 4, 6, 8
+%define PB_0 [pb_0]
+%endif
+
+    mov         r4d,       r4m
+    sub         r0,        r1
+    add         r4d,       r4d
+
+%ifdef PIC
+    lea         r5,        [tabw_ChromaCoeffV]
+    mova        m0,        [r5 + r4 * 8]
+%else
+    mova        m0,        [tabw_ChromaCoeffV + r4 * 8]
+%endif
+
+    mova        m1,        [pw_32]
+
+    lea         r5,        [3 * r1]
+
+%assign x 1
+%rep %1/4
+    movd        m2,        [r0]
+    movd        m3,        [r0 + r1]
+    movd        m4,        [r0 + 2 * r1]
+    movd        m5,        [r0 + r5]
+
+    punpcklbw   m2,        m3
+    punpcklbw   m6,        m4,        m5
+    punpcklbw   m2,        m6
+
+    movhlps     m6,        m2
+    punpcklbw   m2,        PB_0
+    punpcklbw   m6,        PB_0
+    pmaddwd     m2,        m0
+    pmaddwd     m6,        m0
+    packssdw    m2,        m6
+
+    lea         r0,        [r0 + 4 * r1]
+    movd        m6,        [r0]
+
+    punpcklbw   m3,        m4
+    punpcklbw   m7,        m5,        m6
+    punpcklbw   m3,        m7
+
+    movhlps     m7,        m3
+    punpcklbw   m3,        PB_0
+    punpcklbw   m7,        PB_0
+    pmaddwd     m3,        m0
+    pmaddwd     m7,        m0
+    packssdw    m3,        m7
+
+    pshuflw     m7,        m2,        q2301
+    pshufhw     m7,        m7,        q2301
+    paddw       m2,        m7
+    pshuflw     m7,        m3,        q2301
+    pshufhw     m7,        m7,        q2301
+    paddw       m3,        m7
+    psrld       m2,        16
+    psrld       m3,        16
+    packssdw    m2,        m3
+
+    paddw       m2,        m1
+    psraw       m2,        6
+
+    movd        m7,        [r0 + r1]
+
+    punpcklbw   m4,        m5
+    punpcklbw   m3,        m6,        m7
+    punpcklbw   m4,        m3
+
+    movhlps     m3,        m4
+    punpcklbw   m4,        PB_0
+    punpcklbw   m3,        PB_0
+    pmaddwd     m4,        m0
+    pmaddwd     m3,        m0
+    packssdw    m4,        m3
+
+    movd        m3,        [r0 + 2 * r1]
+
+    punpcklbw   m5,        m6
+    punpcklbw   m7,        m3
+    punpcklbw   m5,        m7
+
+    movhlps     m3,        m5
+    punpcklbw   m5,        PB_0
+    punpcklbw   m3,        PB_0
+    pmaddwd     m5,        m0
+    pmaddwd     m3,        m0
+    packssdw    m5,        m3
+
+    pshuflw     m7,        m4,        q2301
+    pshufhw     m7,        m7,        q2301
+    paddw       m4,        m7
+    pshuflw     m7,        m5,        q2301
+    pshufhw     m7,        m7,        q2301
+    paddw       m5,        m7
+    psrld       m4,        16
+    psrld       m5,        16
+    packssdw    m4,        m5
+
+    paddw       m4,        m1
+    psraw       m4,        6
+    packuswb    m2,        m4
+
+    movd        [r2],      m2
+    psrldq      m2,        4
+    movd        [r2 + r3], m2
+    lea         r2,        [r2 + 2 * r3]
+    psrldq      m2,        4
+    movd        [r2],      m2
+    psrldq      m2,        4
+    movd        [r2 + r3], m2
+
+%if x < %1/4
+    lea         r2,        [r2 + 2 * r3]
+%endif
+%assign x x+1
+%endrep
+    RET
+%endmacro
+
+    FILTER_V4_W4_H4_sse2 4
+    FILTER_V4_W4_H4_sse2 8
+    FILTER_V4_W4_H4_sse2 16
+    FILTER_V4_W4_H4_sse2 32
+
+;-----------------------------------------------------------------------------
 ; void interp_4tap_horiz_pp_2x4(pixel *src, intptr_t srcStride, pixel *dst, intptr_t dstStride, int coeffIdx)
 ;-----------------------------------------------------------------------------
 INIT_XMM sse4
diff -r ae9d689acc97 -r e08bcc7339b0 source/common/x86/ipfilter8.h
--- a/source/common/x86/ipfilter8.h	Wed May 06 12:34:58 2015 -0700
+++ b/source/common/x86/ipfilter8.h	Wed May 06 12:43:57 2015 -0700
@@ -909,6 +909,10 @@
 void x265_interp_4tap_vert_pp_2x8_sse2(const pixel *src, intptr_t srcStride, pixel *dst, intptr_t dstStride, int coeffIdx);
 void x265_interp_4tap_vert_pp_2x16_sse2(const pixel *src, intptr_t srcStride, pixel *dst, intptr_t dstStride, int coeffIdx);
 void x265_interp_4tap_vert_pp_4x2_sse2(const pixel *src, intptr_t srcStride, pixel *dst, intptr_t dstStride, int coeffIdx);
+void x265_interp_4tap_vert_pp_4x4_sse2(const pixel *src, intptr_t srcStride, pixel *dst, intptr_t dstStride, int coeffIdx);
+void x265_interp_4tap_vert_pp_4x8_sse2(const pixel *src, intptr_t srcStride, pixel *dst, intptr_t dstStride, int coeffIdx);
+void x265_interp_4tap_vert_pp_4x16_sse2(const pixel *src, intptr_t srcStride, pixel *dst, intptr_t dstStride, int coeffIdx);
+void x265_interp_4tap_vert_pp_4x32_sse2(const pixel *src, intptr_t srcStride, pixel *dst, intptr_t dstStride, int coeffIdx);
 #undef LUMA_FILTERS
 #undef LUMA_SP_FILTERS
 #undef LUMA_SS_FILTERS


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