[x265] [PATCH 1 of 3] asm: interp_4tap_vert_pp sse2
dtyx265 at gmail.com
dtyx265 at gmail.com
Tue May 12 03:41:43 CEST 2015
# HG changeset patch
# User David T Yuen <dtyx265 at gmail.com>
# Date 1431393193 25200
# Node ID 4f8da861a78953a4f16828f14e16c445d3b22cef
# Parent f43b8e01ab507ac36825128322e02a1e06b7cd01
asm: interp_4tap_vert_pp sse2
This replaces c code for 12x16 and 12x32
64-bit
./test/TestBench --testbench interp | grep vpp | grep "\[12x"
chroma_vpp[12x16] 2.84x 8530.57 24230.43
chroma_vpp[12x32] 2.83x 16971.29 48070.71
chroma_vpp[12x16] 2.83x 8554.99 24231.62
diff -r f43b8e01ab50 -r 4f8da861a789 source/common/x86/asm-primitives.cpp
--- a/source/common/x86/asm-primitives.cpp Mon May 11 11:19:43 2015 -0700
+++ b/source/common/x86/asm-primitives.cpp Mon May 11 18:13:13 2015 -0700
@@ -1392,6 +1392,7 @@
p.chroma[X265_CSP_I420].pu[CHROMA_420_8x8].filter_vpp = x265_interp_4tap_vert_pp_8x8_sse2;
p.chroma[X265_CSP_I420].pu[CHROMA_420_8x16].filter_vpp = x265_interp_4tap_vert_pp_8x16_sse2;
p.chroma[X265_CSP_I420].pu[CHROMA_420_8x32].filter_vpp = x265_interp_4tap_vert_pp_8x32_sse2;
+ p.chroma[X265_CSP_I420].pu[CHROMA_420_12x16].filter_vpp = x265_interp_4tap_vert_pp_12x16_sse2;
p.chroma[X265_CSP_I422].pu[CHROMA_422_6x16].filter_vpp = x265_interp_4tap_vert_pp_6x16_sse2;
p.chroma[X265_CSP_I422].pu[CHROMA_422_8x4].filter_vpp = x265_interp_4tap_vert_pp_8x4_sse2;
p.chroma[X265_CSP_I422].pu[CHROMA_422_8x4].filter_vpp = x265_interp_4tap_vert_pp_8x4_sse2;
@@ -1400,10 +1401,12 @@
p.chroma[X265_CSP_I422].pu[CHROMA_422_8x16].filter_vpp = x265_interp_4tap_vert_pp_8x16_sse2;
p.chroma[X265_CSP_I422].pu[CHROMA_422_8x32].filter_vpp = x265_interp_4tap_vert_pp_8x32_sse2;
p.chroma[X265_CSP_I422].pu[CHROMA_422_8x64].filter_vpp = x265_interp_4tap_vert_pp_8x64_sse2;
+ p.chroma[X265_CSP_I422].pu[CHROMA_422_12x32].filter_vpp = x265_interp_4tap_vert_pp_12x32_sse2;
p.chroma[X265_CSP_I444].pu[LUMA_8x4].filter_vpp = x265_interp_4tap_vert_pp_8x4_sse2;
p.chroma[X265_CSP_I444].pu[LUMA_8x8].filter_vpp = x265_interp_4tap_vert_pp_8x8_sse2;
p.chroma[X265_CSP_I444].pu[LUMA_8x16].filter_vpp = x265_interp_4tap_vert_pp_8x16_sse2;
p.chroma[X265_CSP_I444].pu[LUMA_8x32].filter_vpp = x265_interp_4tap_vert_pp_8x32_sse2;
+ p.chroma[X265_CSP_I444].pu[LUMA_12x16].filter_vpp = x265_interp_4tap_vert_pp_12x16_sse2;
#endif
ALL_LUMA_PU(luma_hpp, interp_8tap_horiz_pp, sse2);
diff -r f43b8e01ab50 -r 4f8da861a789 source/common/x86/ipfilter8.asm
--- a/source/common/x86/ipfilter8.asm Mon May 11 11:19:43 2015 -0700
+++ b/source/common/x86/ipfilter8.asm Mon May 11 18:13:13 2015 -0700
@@ -1702,6 +1702,145 @@
FILTER_V4_W8_H8_H16_H32_sse2 8, 64
%endif
+;-----------------------------------------------------------------------------
+; void interp_4tap_vert_pp_12xN(pixel *src, intptr_t srcStride, pixel *dst, intptr_t dstStride, int coeffIdx)
+;-----------------------------------------------------------------------------
+%macro FILTER_V4_W12_H2_sse2 1
+INIT_XMM sse2
+cglobal interp_4tap_vert_pp_12x%1, 4, 6, 11
+ mov r4d, r4m
+ sub r0, r1
+ shl r4d, 5
+ pxor m9, m9
+ mova m6, [pw_32]
+
+%ifdef PIC
+ lea r5, [tab_ChromaCoeffV]
+ mova m1, [r5 + r4]
+ mova m0, [r5 + r4 + 16]
+%else
+ mova m1, [tab_ChromaCoeffV + r4]
+ mova m0, [tab_ChromaCoeffV + r4 + 16]
+%endif
+
+%assign x 1
+%rep %1/2
+ movu m2, [r0]
+ movu m3, [r0 + r1]
+
+ punpcklbw m4, m2, m3
+ punpckhbw m2, m3
+
+ movhlps m8, m4
+ punpcklbw m4, m9
+ punpcklbw m8, m9
+ pmaddwd m4, m1
+ pmaddwd m8, m1
+ packssdw m4, m8
+
+ movhlps m8, m2
+ punpcklbw m2, m9
+ punpcklbw m8, m9
+ pmaddwd m2, m1
+ pmaddwd m8, m1
+ packssdw m2, m8
+
+ lea r0, [r0 + 2 * r1]
+ movu m5, [r0]
+ movu m7, [r0 + r1]
+
+ punpcklbw m10, m5, m7
+ movhlps m8, m10
+ punpcklbw m10, m9
+ punpcklbw m8, m9
+ pmaddwd m10, m0
+ pmaddwd m8, m0
+ packssdw m10, m8
+
+ paddw m4, m10
+
+ punpckhbw m10, m5, m7
+ movhlps m8, m10
+ punpcklbw m10, m9
+ punpcklbw m8, m9
+ pmaddwd m10, m0
+ pmaddwd m8, m0
+ packssdw m10, m8
+
+ paddw m2, m10
+
+ paddw m4, m6
+ psraw m4, 6
+ paddw m2, m6
+ psraw m2, 6
+
+ packuswb m4, m2
+ movh [r2], m4
+ psrldq m4, 8
+ movd [r2 + 8], m4
+
+ punpcklbw m4, m3, m5
+ punpckhbw m3, m5
+
+ movhlps m8, m4
+ punpcklbw m4, m9
+ punpcklbw m8, m9
+ pmaddwd m4, m1
+ pmaddwd m8, m1
+ packssdw m4, m8
+
+ movhlps m8, m4
+ punpcklbw m3, m9
+ punpcklbw m8, m9
+ pmaddwd m3, m1
+ pmaddwd m8, m1
+ packssdw m3, m8
+
+ movu m5, [r0 + 2 * r1]
+ punpcklbw m2, m7, m5
+ punpckhbw m7, m5
+
+ movhlps m8, m2
+ punpcklbw m2, m9
+ punpcklbw m8, m9
+ pmaddwd m2, m0
+ pmaddwd m8, m0
+ packssdw m2, m8
+
+ movhlps m8, m7
+ punpcklbw m7, m9
+ punpcklbw m8, m9
+ pmaddwd m7, m0
+ pmaddwd m8, m0
+ packssdw m7, m8
+
+ paddw m4, m2
+ paddw m3, m7
+
+ paddw m4, m6
+ psraw m4, 6
+ paddw m3, m6
+ psraw m3, 6
+
+ packuswb m4, m3
+ movh [r2 + r3], m4
+ psrldq m4, 8
+ movd [r2 + r3 + 8], m4
+
+%if x < %1/2
+ lea r2, [r2 + 2 * r3]
+%endif
+%assign x x+1
+%endrep
+ RET
+
+%endmacro
+
+%if ARCH_X86_64
+ FILTER_V4_W12_H2_sse2 16
+ FILTER_V4_W12_H2_sse2 32
+%endif
+
%macro FILTER_H4_w2_2 3
movh %2, [srcq - 1]
pshufb %2, %2, Tm0
diff -r f43b8e01ab50 -r 4f8da861a789 source/common/x86/ipfilter8.h
--- a/source/common/x86/ipfilter8.h Mon May 11 11:19:43 2015 -0700
+++ b/source/common/x86/ipfilter8.h Mon May 11 18:13:13 2015 -0700
@@ -924,6 +924,8 @@
void x265_interp_4tap_vert_pp_8x16_sse2(const pixel *src, intptr_t srcStride, pixel *dst, intptr_t dstStride, int coeffIdx);
void x265_interp_4tap_vert_pp_8x32_sse2(const pixel *src, intptr_t srcStride, pixel *dst, intptr_t dstStride, int coeffIdx);
void x265_interp_4tap_vert_pp_8x64_sse2(const pixel *src, intptr_t srcStride, pixel *dst, intptr_t dstStride, int coeffIdx);
+void x265_interp_4tap_vert_pp_12x16_sse2(const pixel *src, intptr_t srcStride, pixel *dst, intptr_t dstStride, int coeffIdx);
+void x265_interp_4tap_vert_pp_12x32_sse2(const pixel *src, intptr_t srcStride, pixel *dst, intptr_t dstStride, int coeffIdx);
#endif
#undef LUMA_FILTERS
#undef LUMA_SP_FILTERS
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