[x265] [PATCH] asm: avx2 code for sad_x3[16xN] for 10 bpp
sumalatha at multicorewareinc.com
sumalatha at multicorewareinc.com
Mon May 18 08:34:53 CEST 2015
# HG changeset patch
# User Sumalatha Polureddy
# Date 1431930810 -19800
# Mon May 18 12:03:30 2015 +0530
# Node ID e9283ef43b7c4eb32a435a835c4ffac2f1163d70
# Parent 8592bf81d0848279fa79cd1487406cb516dffe99
asm: avx2 code for sad_x3[16xN] for 10 bpp
sse2:
sad_x3[ 16x4] 2.93x 680.82 1996.91
sad_x3[ 16x8] 3.03x 1266.26 3834.18
sad_x3[16x12] 3.07x 1834.17 5631.97
sad_x3[16x16] 3.06x 2413.24 7380.88
sad_x3[16x32] 2.82x 5554.36 15654.50
sad_x3[16x64] 2.80x 10161.18 28493.52
avx2:
sad_x3[ 16x4] 4.82x 404.45 1948.78
sad_x3[ 16x8] 5.85x 634.65 3714.40
sad_x3[16x12] 6.17x 885.30 5465.97
sad_x3[16x16] 6.28x 1170.04 7350.87
sad_x3[16x32] 5.34x 2909.76 15547.79
sad_x3[16x64] 6.12x 5071.22 31043.80
diff -r 8592bf81d084 -r e9283ef43b7c source/common/x86/asm-primitives.cpp
--- a/source/common/x86/asm-primitives.cpp Thu May 14 17:12:14 2015 +0530
+++ b/source/common/x86/asm-primitives.cpp Mon May 18 12:03:30 2015 +0530
@@ -1329,6 +1329,13 @@
p.pu[LUMA_64x48].sad = x265_pixel_sad_64x48_avx2;
p.pu[LUMA_64x64].sad = x265_pixel_sad_64x64_avx2;
+ p.pu[LUMA_16x4].sad_x3 = x265_pixel_sad_x3_16x4_avx2;
+ p.pu[LUMA_16x8].sad_x3 = x265_pixel_sad_x3_16x8_avx2;
+ p.pu[LUMA_16x12].sad_x3 = x265_pixel_sad_x3_16x12_avx2;
+ p.pu[LUMA_16x16].sad_x3 = x265_pixel_sad_x3_16x16_avx2;
+ p.pu[LUMA_16x32].sad_x3 = x265_pixel_sad_x3_16x32_avx2;
+ p.pu[LUMA_16x64].sad_x3 = x265_pixel_sad_x3_16x64_avx2;
+
p.pu[LUMA_16x4].convert_p2s = x265_filterPixelToShort_16x4_avx2;
p.pu[LUMA_16x8].convert_p2s = x265_filterPixelToShort_16x8_avx2;
p.pu[LUMA_16x12].convert_p2s = x265_filterPixelToShort_16x12_avx2;
diff -r 8592bf81d084 -r e9283ef43b7c source/common/x86/sad16-a.asm
--- a/source/common/x86/sad16-a.asm Thu May 14 17:12:14 2015 +0530
+++ b/source/common/x86/sad16-a.asm Mon May 18 12:03:30 2015 +0530
@@ -1485,8 +1485,12 @@
SAD_X 4, 8, 4
INIT_YMM avx2
%define XMM_REGS 7
-SAD_X 3, 16, 16
+SAD_X 3, 16, 4
SAD_X 3, 16, 8
+SAD_X 3, 16, 12
+SAD_X 3, 16, 16
+SAD_X 3, 16, 32
+SAD_X 3, 16, 64
%define XMM_REGS 9
SAD_X 4, 16, 16
SAD_X 4, 16, 8
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