[x265] [PATCH 03 of 12] asm: interp_4tap_vert_ps_4xN sse2
dtyx265 at gmail.com
dtyx265 at gmail.com
Tue May 19 02:24:30 CEST 2015
# HG changeset patch
# User David T Yuen <dtyx265 at gmail.com>
# Date 1431990978 25200
# Node ID 660aa8e3a00e3c22543f2fcbc61ff0d81287f9cd
# Parent 54423715e7a28e0ca5874649ebe1a999e4d93463
asm: interp_4tap_vert_ps_4xN sse2
Converted vert_pp_4xN macro to also create ps primitives. This replaces c code for ps with minimal impact on pp.
64-bit
./test/TestBench --testbench interp | grep vp | grep " 4x"
chroma_vpp[ 4x4] 2.10x 1005.01 2107.46
chroma_vps[ 4x4] 1.76x 927.50 1634.98
chroma_vpp[ 4x2] 2.13x 524.99 1117.42
chroma_vps[ 4x2] 1.74x 489.99 854.98
chroma_vpp[ 4x8] 2.29x 1920.00 4400.44
chroma_vps[ 4x8] 1.84x 1792.50 3292.51
chroma_vpp[ 4x16] 2.31x 3765.00 8710.71
chroma_vpp[ 4x8] 2.28x 1927.51 4400.43
chroma_vps[ 4x8] 1.82x 1792.49 3270.18
chroma_vpp[ 4x4] 2.10x 1005.01 2107.44
chroma_vps[ 4x4] 1.76x 927.50 1634.98
chroma_vpp[ 4x16] 2.32x 3755.01 8710.26
chroma_vps[ 4x16] 1.90x 3522.50 6698.16
chroma_vpp[ 4x32] 2.29x 7415.00 16995.20
chroma_vpp[ 4x4] 2.10x 1005.01 2107.46
chroma_vps[ 4x4] 1.76x 927.50 1634.98
chroma_vpp[ 4x8] 2.28x 1927.51 4400.45
chroma_vps[ 4x8] 1.82x 1792.49 3270.18
chroma_vpp[ 4x16] 2.31x 3765.00 8710.56
chroma_vps[ 4x16] 1.90x 3522.49 6697.70
32-bit
./test/TestBench --testbench interp | grep vp | grep " 4x"
chroma_vpp[ 4x4] 2.40x 1144.99 2747.42
chroma_vps[ 4x4] 2.47x 1092.48 2702.46
chroma_vpp[ 4x2] 2.44x 579.98 1414.91
chroma_vps[ 4x2] 2.37x 555.84 1314.96
chroma_vpp[ 4x8] 2.61x 2165.00 5640.12
chroma_vps[ 4x8] 2.07x 2030.00 4200.76
chroma_vpp[ 4x16] 2.64x 4207.50 11097.51
chroma_vpp[ 4x8] 2.61x 2159.99 5640.12
chroma_vps[ 4x8] 2.07x 2027.50 4200.16
chroma_vpp[ 4x4] 2.35x 1170.00 2747.49
chroma_vps[ 4x4] 2.49x 1086.25 2702.46
chroma_vpp[ 4x16] 2.64x 4202.50 11097.51
chroma_vps[ 4x16] 2.05x 3927.50 8034.64
chroma_vpp[ 4x32] 2.64x 8254.99 21817.51
chroma_vpp[ 4x4] 2.40x 1144.97 2747.42
chroma_vps[ 4x4] 2.47x 1092.50 2702.42
chroma_vpp[ 4x8] 2.61x 2159.99 5640.30
chroma_vps[ 4x8] 2.07x 2028.45 4200.50
chroma_vpp[ 4x16] 2.64x 4207.49 11097.51
chroma_vps[ 4x16] 2.04x 3929.99 8035.64
diff -r 54423715e7a2 -r 660aa8e3a00e source/common/x86/asm-primitives.cpp
--- a/source/common/x86/asm-primitives.cpp Mon May 18 16:07:30 2015 -0700
+++ b/source/common/x86/asm-primitives.cpp Mon May 18 16:16:18 2015 -0700
@@ -1451,7 +1451,15 @@
p.chroma[X265_CSP_I420].pu[CHROMA_420_2x4].filter_vps = x265_interp_4tap_vert_ps_2x4_sse2;
p.chroma[X265_CSP_I420].pu[CHROMA_420_2x8].filter_vps = x265_interp_4tap_vert_ps_2x8_sse2;
p.chroma[X265_CSP_I420].pu[CHROMA_420_4x2].filter_vps = x265_interp_4tap_vert_ps_4x2_sse2;
+ p.chroma[X265_CSP_I420].pu[CHROMA_420_4x4].filter_vps = x265_interp_4tap_vert_ps_4x4_sse2;
+ p.chroma[X265_CSP_I420].pu[CHROMA_420_4x8].filter_vps = x265_interp_4tap_vert_ps_4x8_sse2;
p.chroma[X265_CSP_I422].pu[CHROMA_422_2x16].filter_vps = x265_interp_4tap_vert_ps_2x16_sse2;
+ p.chroma[X265_CSP_I422].pu[CHROMA_422_4x4].filter_vps = x265_interp_4tap_vert_ps_4x4_sse2;
+ p.chroma[X265_CSP_I422].pu[CHROMA_422_4x8].filter_vps = x265_interp_4tap_vert_ps_4x8_sse2;
+ p.chroma[X265_CSP_I422].pu[CHROMA_422_4x16].filter_vps = x265_interp_4tap_vert_ps_4x16_sse2;
+ p.chroma[X265_CSP_I444].pu[LUMA_4x4].filter_vps = x265_interp_4tap_vert_ps_4x4_sse2;
+ p.chroma[X265_CSP_I444].pu[LUMA_4x8].filter_vps = x265_interp_4tap_vert_ps_4x8_sse2;
+ p.chroma[X265_CSP_I444].pu[LUMA_4x16].filter_vps = x265_interp_4tap_vert_ps_4x16_sse2;
#if X86_64
p.chroma[X265_CSP_I420].pu[CHROMA_420_6x8].filter_vpp = x265_interp_4tap_vert_pp_6x8_sse2;
p.chroma[X265_CSP_I420].pu[CHROMA_420_8x2].filter_vpp = x265_interp_4tap_vert_pp_8x2_sse2;
diff -r 54423715e7a2 -r 660aa8e3a00e source/common/x86/ipfilter8.asm
--- a/source/common/x86/ipfilter8.asm Mon May 18 16:07:30 2015 -0700
+++ b/source/common/x86/ipfilter8.asm Mon May 18 16:16:18 2015 -0700
@@ -1111,15 +1111,15 @@
FILTER_V2_W4_H4_sse2 ps
;-----------------------------------------------------------------------------
-; void interp_4tap_vert_pp_%1x%2(pixel *src, intptr_t srcStride, pixel *dst, intptr_t dstStride, int coeffIdx)
-;-----------------------------------------------------------------------------
-%macro FILTER_V4_W4_H4_sse2 1
+; void interp_4tap_vert_%1_4x%2(pixel *src, intptr_t srcStride, pixel *dst, intptr_t dstStride, int coeffIdx)
+;-----------------------------------------------------------------------------
+%macro FILTER_V4_W4_H4_sse2 2
INIT_XMM sse2
%if ARCH_X86_64
-cglobal interp_4tap_vert_pp_4x%1, 4, 6, 9
+cglobal interp_4tap_vert_%1_4x%2, 4, 6, 9
pxor m8, m8
%else
-cglobal interp_4tap_vert_pp_4x%1, 4, 6, 8
+cglobal interp_4tap_vert_%1_4x%2, 4, 6, 8
%endif
mov r4d, r4m
@@ -1132,12 +1132,19 @@
movh m0, [tabw_ChromaCoeff + r4 * 8]
%endif
+%ifidn %1,pp
mova m1, [pw_32]
+%elifidn %1,ps
+ add r3d, r3d
+ mova m1, [pw_2000]
+%endif
+
lea r5, [3 * r1]
+ lea r4, [3 * r3]
punpcklqdq m0, m0
%assign x 1
-%rep %1/4
+%rep %2/4
movd m2, [r0]
movd m3, [r0 + r1]
movd m4, [r0 + 2 * r1]
@@ -1174,12 +1181,24 @@
pshuflw m7, m3, q2301
pshufhw m7, m7, q2301
paddw m3, m7
+
+%ifidn %1,pp
psrld m2, 16
psrld m3, 16
packssdw m2, m3
-
paddw m2, m1
psraw m2, 6
+%elifidn %1,ps
+ psrldq m2, 2
+ psrldq m3, 2
+ pshufd m2, m2, q3120
+ pshufd m3, m3, q3120
+
+ psubw m2, m1
+ psubw m3, m1
+ movh [r2], m2
+ movh [r2 + r3], m3
+%endif
movd m7, [r0 + r1]
@@ -1213,6 +1232,8 @@
pshuflw m7, m5, q2301
pshufhw m7, m7, q2301
paddw m5, m7
+
+%ifidn %1,pp
psrld m4, 16
psrld m5, 16
packssdw m4, m5
@@ -1224,24 +1245,41 @@
movd [r2], m2
psrldq m2, 4
movd [r2 + r3], m2
- lea r2, [r2 + 2 * r3]
psrldq m2, 4
- movd [r2], m2
+ movd [r2 + 2 * r3], m2
psrldq m2, 4
- movd [r2 + r3], m2
-
-%if x < %1/4
- lea r2, [r2 + 2 * r3]
-%endif
+ movd [r2 + r4], m2
+%elifidn %1,ps
+ psrldq m4, 2
+ psrldq m5, 2
+ pshufd m4, m4, q3120
+ pshufd m5, m5, q3120
+
+ psubw m4, m1
+ psubw m5, m1
+ movh [r2 + 2 * r3], m4
+ movh [r2 + r4], m5
+%endif
+
+%if x < %2/4
+ lea r2, [r2 + 4 * r3]
+%endif
+
%assign x x+1
%endrep
RET
-%endmacro
-
- FILTER_V4_W4_H4_sse2 4
- FILTER_V4_W4_H4_sse2 8
- FILTER_V4_W4_H4_sse2 16
- FILTER_V4_W4_H4_sse2 32
+
+%endmacro
+
+ FILTER_V4_W4_H4_sse2 pp, 4
+ FILTER_V4_W4_H4_sse2 pp, 8
+ FILTER_V4_W4_H4_sse2 pp, 16
+ FILTER_V4_W4_H4_sse2 pp, 32
+
+ FILTER_V4_W4_H4_sse2 ps, 4
+ FILTER_V4_W4_H4_sse2 ps, 8
+ FILTER_V4_W4_H4_sse2 ps, 16
+ FILTER_V4_W4_H4_sse2 ps, 32
;-----------------------------------------------------------------------------
;void interp_4tap_vert_pp_6x8(pixel *src, intptr_t srcStride, pixel *dst, intptr_t dstStride, int coeffIdx)
diff -r 54423715e7a2 -r 660aa8e3a00e source/common/x86/ipfilter8.h
--- a/source/common/x86/ipfilter8.h Mon May 18 16:07:30 2015 -0700
+++ b/source/common/x86/ipfilter8.h Mon May 18 16:16:18 2015 -0700
@@ -917,6 +917,10 @@
void x265_interp_4tap_vert_ps_2x8_sse2(const pixel* src, intptr_t srcStride, int16_t* dst, intptr_t dstStride, int coeffIdx);
void x265_interp_4tap_vert_ps_2x16_sse2(const pixel* src, intptr_t srcStride, int16_t* dst, intptr_t dstStride, int coeffIdx);
void x265_interp_4tap_vert_ps_4x2_sse2(const pixel* src, intptr_t srcStride, int16_t* dst, intptr_t dstStride, int coeffIdx);
+void x265_interp_4tap_vert_ps_4x4_sse2(const pixel* src, intptr_t srcStride, int16_t* dst, intptr_t dstStride, int coeffIdx);
+void x265_interp_4tap_vert_ps_4x8_sse2(const pixel* src, intptr_t srcStride, int16_t* dst, intptr_t dstStride, int coeffIdx);
+void x265_interp_4tap_vert_ps_4x16_sse2(const pixel* src, intptr_t srcStride, int16_t* dst, intptr_t dstStride, int coeffIdx);
+void x265_interp_4tap_vert_ps_4x32_sse2(const pixel* src, intptr_t srcStride, int16_t* dst, intptr_t dstStride, int coeffIdx);
#ifdef X86_64
void x265_interp_4tap_vert_pp_6x8_sse2(const pixel *src, intptr_t srcStride, pixel *dst, intptr_t dstStride, int coeffIdx);
void x265_interp_4tap_vert_pp_6x16_sse2(const pixel *src, intptr_t srcStride, pixel *dst, intptr_t dstStride, int coeffIdx);
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