[x265] [PATCH 2 of 2] asm: interp_4tap_vert_pX_4xN sse2

[chen]

Why x64 only? r4 always free in both x86 and x64

At 2015-05-20 07:33:14,dtyx265 at gmail.com wrote:
># HG changeset patch
># User David T Yuen <dtyx265 at gmail.com>
># Date 1432078001 25200
># Node ID 509f7cbf8e09d6ddec4aa58040cfd206879d59e7
># Parent  3e07cba4b2034db2b819b2e11e98ee4b851d52b5
>asm: interp_4tap_vert_pX_4xN sse2
>
>Improved register usage for addressing of output.  This improvement helps 64-bit .7% to 2.5% but hurt 32-bit performance so I made it 64-bit only.
>Also added interp_4tap_vert_ps_4x32 in primitives setup.
>
>diff -r 3e07cba4b203 -r 509f7cbf8e09 source/common/x86/asm-primitives.cpp
>--- a/source/common/x86/asm-primitives.cpp	Tue May 19 14:27:04 2015 -0700
>+++ b/source/common/x86/asm-primitives.cpp	Tue May 19 16:26:41 2015 -0700
>@@ -1482,6 +1482,7 @@
>         p.chroma[X265_CSP_I422].pu[CHROMA_422_4x4].filter_vps = x265_interp_4tap_vert_ps_4x4_sse2;
>         p.chroma[X265_CSP_I422].pu[CHROMA_422_4x8].filter_vps = x265_interp_4tap_vert_ps_4x8_sse2;
>         p.chroma[X265_CSP_I422].pu[CHROMA_422_4x16].filter_vps = x265_interp_4tap_vert_ps_4x16_sse2;
>+        p.chroma[X265_CSP_I422].pu[CHROMA_422_4x32].filter_vps = x265_interp_4tap_vert_ps_4x32_sse2;
>         p.chroma[X265_CSP_I444].pu[LUMA_4x4].filter_vps = x265_interp_4tap_vert_ps_4x4_sse2;
>         p.chroma[X265_CSP_I444].pu[LUMA_4x8].filter_vps = x265_interp_4tap_vert_ps_4x8_sse2;
>         p.chroma[X265_CSP_I444].pu[LUMA_4x16].filter_vps = x265_interp_4tap_vert_ps_4x16_sse2;
>diff -r 3e07cba4b203 -r 509f7cbf8e09 source/common/x86/ipfilter8.asm
>--- a/source/common/x86/ipfilter8.asm	Tue May 19 14:27:04 2015 -0700
>+++ b/source/common/x86/ipfilter8.asm	Tue May 19 16:26:41 2015 -0700
>@@ -1138,6 +1138,9 @@
>     mova        m1,        [pw_2000]
> %endif
> 
>+%if ARCH_X86_64
>+    lea         r4,        [3 * r3]
>+%endif
>     lea         r5,        [3 * r1]
>     punpcklqdq  m0,        m0
> 
>@@ -1243,11 +1246,23 @@
>     movd        [r2],      m2
>     psrldq      m2,        4
>     movd        [r2 + r3], m2
>+    psrldq      m2,        4
>+%if ARCH_X86_64
>+    movd        [r2 + 2 * r3],      m2
>+    psrldq      m2,        4
>+    movd        [r2 + r4], m2
>+%if x < %2/4
>+    lea         r2,        [r2 + 4 * r3]
>+%endif
>+%else
>     lea         r2,        [r2 + 2 * r3]
>-    psrldq      m2,        4
>     movd        [r2],      m2
>     psrldq      m2,        4
>     movd        [r2 + r3], m2
>+%if x < %2/4
>+    lea         r2,        [r2 + 2 * r3]
>+%endif
>+%endif
> %elifidn %1,ps
>     psrldq      m4,        2
>     psrldq      m5,        2
>@@ -1255,14 +1270,25 @@
>     pshufd      m5,        m5, q3120
>     punpcklqdq  m4,        m5
>     psubw       m4,        m1
>+%if ARCH_X86_64
>+    movh        [r2 + 2 * r3],      m4
>+    movhps      [r2 + r4], m4
>+%if x < %2/4
>+    lea         r2,        [r2 + 4 * r3]
>+%endif
>+%else
>     lea         r2,        [r2 + 2 * r3]
>     movh        [r2],      m4
>     movhps      [r2 + r3], m4
>-%endif
>-
> %if x < %2/4
>     lea         r2,        [r2 + 2 * r3]
> %endif
>+%endif
>+%endif
>+
>+; %if x < %2/4
>+;     lea         r2,        [r2 + 4 * r3]
>+; %endif
> 
> %assign x x+1
> %endrep
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