[x265] [PATCH] asm: avx2 10bit code for chroma_hpp[12x16], [24x32] for i420
rajesh at multicorewareinc.com
rajesh at multicorewareinc.com
Thu May 28 12:23:29 CEST 2015
# HG changeset patch
# User Rajesh Paulraj<rajesh at multicorewareinc.com>
# Date 1432805111 -19800
# Thu May 28 14:55:11 2015 +0530
# Node ID f1ab5ba015c00dc2bfb8927e047c0c6d5f974144
# Parent 3c2a050acbd7ee16f44f19ce170a701774c0e460
asm: avx2 10bit code for chroma_hpp[12x16],[24x32] for i420
avx2:
chroma_hpp[12x16] 5.30x 2590.83 13729.57
chroma_hpp[24x32] 6.93x 7998.90 55392.53
sse4:
chroma_hpp[12x16] 5.36x 2763.04 14810.12
chroma_hpp[24x32] 5.65x 9505.09 53707.21
diff -r 3c2a050acbd7 -r f1ab5ba015c0 source/common/x86/asm-primitives.cpp
--- a/source/common/x86/asm-primitives.cpp Wed May 27 12:54:50 2015 +0530
+++ b/source/common/x86/asm-primitives.cpp Thu May 28 14:55:11 2015 +0530
@@ -1542,6 +1542,8 @@
p.chroma[X265_CSP_I420].pu[CHROMA_420_32x16].filter_hpp = x265_interp_4tap_horiz_pp_32x16_avx2;
p.chroma[X265_CSP_I420].pu[CHROMA_420_32x24].filter_hpp = x265_interp_4tap_horiz_pp_32x24_avx2;
p.chroma[X265_CSP_I420].pu[CHROMA_420_32x32].filter_hpp = x265_interp_4tap_horiz_pp_32x32_avx2;
+ p.chroma[X265_CSP_I420].pu[CHROMA_420_12x16].filter_hpp = x265_interp_4tap_horiz_pp_12x16_avx2;
+ p.chroma[X265_CSP_I420].pu[CHROMA_420_24x32].filter_hpp = x265_interp_4tap_horiz_pp_24x32_avx2;
if (cpuMask & X265_CPU_BMI2)
p.scanPosLast = x265_scanPosLast_avx2_bmi2;
diff -r 3c2a050acbd7 -r f1ab5ba015c0 source/common/x86/ipfilter16.asm
--- a/source/common/x86/ipfilter16.asm Wed May 27 12:54:50 2015 +0530
+++ b/source/common/x86/ipfilter16.asm Thu May 28 14:55:11 2015 +0530
@@ -2666,6 +2666,155 @@
IPFILTER_CHROMA_avx2_32xN 24
IPFILTER_CHROMA_avx2_32xN 32
+;-------------------------------------------------------------------------------------------------------------
+; void interp_4tap_horiz_pp(pixel *src, intptr_t srcStride, int16_t *dst, intptr_t dstStride, int coeffIdx
+;-------------------------------------------------------------------------------------------------------------
+INIT_YMM avx2
+%macro IPFILTER_CHROMA_avx2_12xN 1
+%if ARCH_X86_64
+cglobal interp_4tap_horiz_pp_12x%1, 5,6,8
+ add r1d, r1d
+ add r3d, r3d
+ sub r0, 2
+ mov r4d, r4m
+%ifdef PIC
+ lea r5, [tab_ChromaCoeff]
+ vpbroadcastq m0, [r5 + r4 * 8]
+%else
+ vpbroadcastq m0, [tab_ChromaCoeff + r4 * 8]
+%endif
+ mova m1, [interp8_hpp_shuf]
+ vpbroadcastd m2, [pd_32]
+ pxor m5, m5
+ mova m6, [idct8_shuf2]
+ mova m7, [pw_pixel_max]
+
+ mov r4d, %1
+.loop:
+ vbroadcasti128 m3, [r0]
+ vbroadcasti128 m4, [r0 + 8]
+ pshufb m3, m1
+ pshufb m4, m1
+
+ pmaddwd m3, m0
+ pmaddwd m4, m0
+ phaddd m3, m4
+ paddd m3, m2
+ psrad m3, 6 ; m3 = DWORD[7 6 3 2 5 4 1 0]
+
+ packusdw m3, m3
+ vpermq m3, m3, q2020
+ pshufb xm3, xm6 ; m3 = WORD[7 6 5 4 3 2 1 0]
+ CLIPW xm3, xm5, xm7
+ movu [r2], xm3
+
+ vbroadcasti128 m3, [r0 + 16]
+ vbroadcasti128 m4, [r0 + 24]
+ pshufb m3, m1
+ pshufb m4, m1
+
+ pmaddwd m3, m0
+ pmaddwd m4, m0
+ phaddd m3, m4
+ paddd m3, m2
+ psrad m3, 6 ; m3 = DWORD[7 6 3 2 5 4 1 0]
+
+ packusdw m3, m3
+ vpermq m3, m3, q2020
+ pshufb xm3, xm6 ; m3 = WORD[7 6 5 4 3 2 1 0]
+ CLIPW xm3, xm5, xm7
+ movq [r2 + 16], xm3
+
+ add r0, r1
+ add r2, r3
+ dec r4d
+ jnz .loop
+ RET
+%endif
+%endmacro
+IPFILTER_CHROMA_avx2_12xN 16
+IPFILTER_CHROMA_avx2_12xN 32
+
+;-------------------------------------------------------------------------------------------------------------
+; void interp_4tap_horiz_pp(pixel *src, intptr_t srcStride, int16_t *dst, intptr_t dstStride, int coeffIdx
+;-------------------------------------------------------------------------------------------------------------
+INIT_YMM avx2
+%macro IPFILTER_CHROMA_avx2_24xN 1
+%if ARCH_X86_64
+cglobal interp_4tap_horiz_pp_24x%1, 5,6,9
+ add r1d, r1d
+ add r3d, r3d
+ sub r0, 2
+ mov r4d, r4m
+%ifdef PIC
+ lea r5, [tab_ChromaCoeff]
+ vpbroadcastq m0, [r5 + r4 * 8]
+%else
+ vpbroadcastq m0, [tab_ChromaCoeff + r4 * 8]
+%endif
+ mova m1, [interp8_hpp_shuf]
+ vpbroadcastd m2, [pd_32]
+ pxor m5, m5
+ mova m6, [idct8_shuf2]
+ mova m7, [pw_pixel_max]
+
+ mov r4d, %1
+.loop:
+ vbroadcasti128 m3, [r0]
+ vbroadcasti128 m4, [r0 + 8]
+ pshufb m3, m1
+ pshufb m4, m1
+
+ pmaddwd m3, m0
+ pmaddwd m4, m0
+ phaddd m3, m4
+ paddd m3, m2
+ psrad m3, 6
+
+ vbroadcasti128 m4, [r0 + 16]
+ vbroadcasti128 m8, [r0 + 24]
+ pshufb m4, m1
+ pshufb m8, m1
+
+ pmaddwd m4, m0
+ pmaddwd m8, m0
+ phaddd m4, m8
+ paddd m4, m2
+ psrad m4, 6
+
+ packusdw m3, m4
+ vpermq m3, m3, q3120
+ pshufb m3, m6
+ CLIPW m3, m5, m7
+ movu [r2], m3
+
+ vbroadcasti128 m3, [r0 + 32]
+ vbroadcasti128 m4, [r0 + 40]
+ pshufb m3, m1
+ pshufb m4, m1
+
+ pmaddwd m3, m0
+ pmaddwd m4, m0
+ phaddd m3, m4
+ paddd m3, m2
+ psrad m3, 6
+
+ packusdw m3, m3
+ vpermq m3, m3, q2020
+ pshufb xm3, xm6
+ CLIPW xm3, xm5, xm7
+ movu [r2 + 32], xm3
+
+ add r0, r1
+ add r2, r3
+ dec r4d
+ jnz .loop
+ RET
+%endif
+%endmacro
+IPFILTER_CHROMA_avx2_24xN 32
+IPFILTER_CHROMA_avx2_24xN 64
+
;-----------------------------------------------------------------------------------------------------------------
; void interp_4tap_vert_%3_%1x%2(int16_t *src, intptr_t srcStride, int16_t *dst, intptr_t dstStride, int coeffIdx)
;-----------------------------------------------------------------------------------------------------------------
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