[x265] [PATCH] asm: fix intrapred_planar16x16 sse4 code for main12

chen chenm003 at 163.com
Mon Oct 19 18:05:42 CEST 2015




At 2015-10-19 18:43:57,dnyaneshwar at multicorewareinc.com wrote:
># HG changeset patch
># User Dnyaneshwar G <dnyaneshwar at multicorewareinc.com>
># Date 1445245458 -19800
>#      Mon Oct 19 14:34:18 2015 +0530
># Node ID 76d4fc7264a0d22218db30f65bb58095c294db1b
># Parent  04575a459a160162391fcf1a12e8e6f2e81e95b4
>asm: fix intrapred_planar16x16 sse4 code for main12
>
>diff -r 04575a459a16 -r 76d4fc7264a0 source/common/x86/asm-primitives.cpp
>--- a/source/common/x86/asm-primitives.cpp	Wed Sep 30 11:22:16 2015 +0530
>+++ b/source/common/x86/asm-primitives.cpp	Mon Oct 19 14:34:18 2015 +0530
>@@ -1145,8 +1145,9 @@
>         p.cu[BLOCK_4x4].intra_pred[PLANAR_IDX] = PFX(intra_pred_planar4_sse4);
>         p.cu[BLOCK_8x8].intra_pred[PLANAR_IDX] = PFX(intra_pred_planar8_sse4);
> 
>+        p.cu[BLOCK_16x16].intra_pred[PLANAR_IDX] = PFX(intra_pred_planar16_sse4);
>+
> #if X265_DEPTH <= 10
>-        p.cu[BLOCK_16x16].intra_pred[PLANAR_IDX] = PFX(intra_pred_planar16_sse4);
>         p.cu[BLOCK_32x32].intra_pred[PLANAR_IDX] = PFX(intra_pred_planar32_sse4);
> #endif
>         ALL_LUMA_TU_S(intra_pred[DC_IDX], intra_pred_dc, sse4);
>diff -r 04575a459a16 -r 76d4fc7264a0 source/common/x86/const-a.asm
>--- a/source/common/x86/const-a.asm	Wed Sep 30 11:22:16 2015 +0530
>+++ b/source/common/x86/const-a.asm	Mon Oct 19 14:34:18 2015 +0530
>@@ -122,6 +122,7 @@
> const pd_2,                 times  8 dd 2
> const pd_4,                 times  4 dd 4
> const pd_8,                 times  4 dd 8
>+const pd_15,                times  8 dd 15
> const pd_16,                times  8 dd 16
> const pd_31,                times  4 dd 31
> const pd_32,                times  8 dd 32
>@@ -136,7 +137,8 @@
> const pd_524416,            times  4 dd 524416
> const pd_n32768,            times  8 dd 0xffff8000
> const pd_n131072,           times  4 dd 0xfffe0000
>-
>+const pd_planar16_mul,      times  1 dd  15,  14,  13,  12,  11,  10,   9,   8,   7,   6,   5,   4,   3,   2,   1,   0
>+const pd_planar16_mul1,     times  1 dd   1,   2,   3,   4,   5,   6,   7,   8,   9,  10,  11,  12,  13,  14,  15,  16
> const trans8_shuf,          times  1 dd   0,   4,   1,   5,   2,   6,   3,   7
> 
> const popcnt_table
>diff -r 04575a459a16 -r 76d4fc7264a0 source/common/x86/intrapred16.asm
>--- a/source/common/x86/intrapred16.asm	Wed Sep 30 11:22:16 2015 +0530
>+++ b/source/common/x86/intrapred16.asm	Mon Oct 19 14:34:18 2015 +0530
>@@ -109,6 +109,7 @@
> cextern pw_16
> cextern pw_31
> cextern pw_32
>+cextern pd_15
> cextern pd_16
> cextern pd_31
> cextern pd_32
>@@ -123,6 +124,8 @@
> cextern pb_unpackwq1
> cextern pb_unpackwq2
> cextern pw_planar16_mul
>+cextern pd_planar16_mul
>+cextern pd_planar16_mul1
> cextern pw_planar32_mul
> 
> ;-----------------------------------------------------------------------------------
>@@ -2216,6 +2219,110 @@
> ; void intra_pred_planar(pixel* dst, intptr_t dstStride, pixel*srcPix, int, int filter)
> ;---------------------------------------------------------------------------------------
> INIT_XMM sse4
>+%if ARCH_X86_64 == 1 && BIT_DEPTH == 12
>+cglobal intra_pred_planar16, 3,5,12
>+    add             r1d, r1d
>+
>+    pmovzxwd        m2, [r2 + 2]
>+    pmovzxwd        m7, [r2 + 10]
>+    pmovzxwd        m10, [r2 + 18]
>+    pmovzxwd        m0, [r2 + 26]
>+
>+    movzx           r3d, word [r2 + 34]                     ; topRight   = above[16]
>+    movzx           r4d, word [r2 + 98]                     ; bottomLeft = left[16]
move below

>+
>+    movd            m3, r3d
>+    pshufd          m3, m3, 0                               ; topRight
>+
>+    pmulld          m8, m3, [pd_planar16_mul1 + 3*mmsize]   ; (x + 1) * topRight
>+    pmulld          m4, m3, [pd_planar16_mul1 + 2*mmsize]   ; (x + 1) * topRight
>+    pmulld          m9, m3, [pd_planar16_mul1 + 1*mmsize]   ; (x + 1) * topRight
>+    pmulld          m3, m3, [pd_planar16_mul1 + 0*mmsize]   ; (x + 1) * topRight
we can use r4 on above address operator

>+
>+    pmulld          m1, m2,  [pd_15]                        ; (blkSize - 1 - y) * above[x]
>+    pmulld          m6, m7,  [pd_15]                        ; (blkSize - 1 - y) * above[x]
>+    pmulld          m5, m10, [pd_15]                        ; (blkSize - 1 - y) * above[x]
>+    pmulld          m11, m0, [pd_15]                        ; (blkSize - 1 - y) * above[x]
>+
>+    paddd           m3, [pd_16]
>+    paddd           m9, [pd_16]
>+    paddd           m4, [pd_16]
>+    paddd           m8, [pd_16]
the constant use more than 4 times, so we can load it into register, we have many free/reuse registers in here

>+
>+    paddd           m4, m5
>+    paddd           m3, m1
>+    paddd           m8, m11
>+    paddd           m9, m6
>+
>+    movd            m6, r4d
if we use move above r4d operator here, we can reuse r4d for address operator

>+    pshufd          m6, m6, 0                               ; bottomLeft
>+
>+    paddd           m4, m6
>+    paddd           m3, m6
>+    paddd           m8, m6
>+    paddd           m9, m6
>+
>+    psubd           m1, m6, m0                              ; column 12-15
>+    psubd           m11, m6, m10                            ; column 8-11
>+    psubd           m10, m6, m7                             ; column 4-7
>+    psubd           m6, m2                                  ; column 0-3
>+
>+    add             r2, 66
>+
>+%macro INTRA_PRED_PLANAR16 1
>+    movzx           r3d, word [r2]
>+    movd            m5, r3d
>+    pshufd          m5, m5, 0
>+
>+    pmulld          m0, m5, [pd_planar16_mul + 3*mmsize]    ; column 12-15
>+    pmulld          m2, m5, [pd_planar16_mul + 2*mmsize]    ; column 8-11
>+    pmulld          m7, m5, [pd_planar16_mul + 1*mmsize]    ; column 4-7
>+    pmulld          m5, m5, [pd_planar16_mul + 0*mmsize]    ; column 0-3
>+
>+    paddd           m0, m8
>+    paddd           m2, m4
>+    paddd           m7, m9
>+    paddd           m5, m3
>+
>+    paddd           m8, m1
>+    paddd           m4, m11
>+    paddd           m9, m10
>+    paddd           m3, m6
>+
>+    psrad           m0, 5
>+    psrad           m2, 5
>+    psrad           m7, 5
>+    psrad           m5, 5
>+
>+    packusdw        m2, m0
>+    packusdw        m5, m7
>+    movu            [r0], m5
>+    movu            [r0 + mmsize], m2
>+
>+    add             r2, 2
>+    lea             r0, [r0 + r1]
>+%endmacro
>+
>+    INTRA_PRED_PLANAR16 0
>+    INTRA_PRED_PLANAR16 1
>+    INTRA_PRED_PLANAR16 2
>+    INTRA_PRED_PLANAR16 3
>+    INTRA_PRED_PLANAR16 4
>+    INTRA_PRED_PLANAR16 5
>+    INTRA_PRED_PLANAR16 6
>+    INTRA_PRED_PLANAR16 7
>+    INTRA_PRED_PLANAR16 8
>+    INTRA_PRED_PLANAR16 9
>+    INTRA_PRED_PLANAR16 10
>+    INTRA_PRED_PLANAR16 11
>+    INTRA_PRED_PLANAR16 12
>+    INTRA_PRED_PLANAR16 13
>+    INTRA_PRED_PLANAR16 14
>+    INTRA_PRED_PLANAR16 15
>+    RET
>+
>+%else
>+; code for BIT_DEPTH == 10
> cglobal intra_pred_planar16, 3,3,8
>     add             r1, r1
>     movu            m2, [r2 + 2]
>@@ -2293,6 +2400,7 @@
>     INTRA_PRED_PLANAR16 14
>     INTRA_PRED_PLANAR16 15
>     RET
>+%endif
> 
> ;---------------------------------------------------------------------------------------
> ; void intra_pred_planar(pixel* dst, intptr_t dstStride, pixel*srcPix, int, int filter)
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