[x265] [PATCH] asm: fix sse_pp[32x64] sse2 asm for 12 bit

[chen]

At 2015-09-07 19:57:11,ramya at multicorewareinc.com wrote:
># HG changeset patch
># User Ramya Sriraman <ramya at multicorewareinc.com>
># Date 1441626889 -19800
>#      Mon Sep 07 17:24:49 2015 +0530
># Node ID 2212b9cb4ea5725639cdcbae49c7b530aa79ce1c
># Parent  f622f46b2ce87d6f30d937de79c1de94a5d0ee54
>asm: fix sse_pp[32x64] sse2 asm for 12 bit
>
>diff -r f622f46b2ce8 -r 2212b9cb4ea5 source/common/x86/asm-primitives.cpp
>--- a/source/common/x86/asm-primitives.cpp	Wed Aug 26 17:06:25 2015 +0530
>+++ b/source/common/x86/asm-primitives.cpp	Mon Sep 07 17:24:49 2015 +0530
>@@ -1000,11 +1000,10 @@
>         p.chroma[X265_CSP_I422].cu[BLOCK_422_4x8].sse_pp = (pixel_sse_t)PFX(pixel_ssd_ss_4x8_mmx2);
>         p.chroma[X265_CSP_I422].cu[BLOCK_422_8x16].sse_pp = (pixel_sse_t)PFX(pixel_ssd_ss_8x16_sse2);
>         p.chroma[X265_CSP_I422].cu[BLOCK_422_16x32].sse_pp = (pixel_sse_t)PFX(pixel_ssd_ss_16x32_sse2);
>-
>+        p.chroma[X265_CSP_I422].cu[BLOCK_422_32x64].sse_pp = (pixel_sse_t)PFX(pixel_ssd_ss_32x64_sse2);
> #if X265_DEPTH <= 10
>         p.cu[BLOCK_4x4].sse_ss = PFX(pixel_ssd_ss_4x4_mmx2);
>         ALL_LUMA_CU(sse_ss, pixel_ssd_ss, sse2);
>-        p.chroma[X265_CSP_I422].cu[BLOCK_422_32x64].sse_pp = (pixel_sse_t)PFX(pixel_ssd_ss_32x64_sse2);
> #endif
>         p.cu[BLOCK_4x4].dct = PFX(dct4_sse2);
>         p.cu[BLOCK_8x8].dct = PFX(dct8_sse2);
>diff -r f622f46b2ce8 -r 2212b9cb4ea5 source/common/x86/ssd-a.asm
>--- a/source/common/x86/ssd-a.asm	Wed Aug 26 17:06:25 2015 +0530
>+++ b/source/common/x86/ssd-a.asm	Mon Sep 07 17:24:49 2015 +0530
>@@ -125,6 +125,61 @@
>     RET
> %endmacro
> 
>+; Function to find ssd for 32x16 block, sse2, 12 bit depth
>+; Defined sepeartely to be called from SSD_ONE_32 macro
>+INIT_XMM sse2
>+cglobal ssd_ss_32x16
>+    pxor    m8, m8
>+    mov     r4d, 16
need more space, ident to below code

>+.loop:
>+    movu        m0, [r0]
>+    movu        m1, [r0+mmsize]
>+    movu        m2, [r0+2*mmsize]
>+    movu        m3, [r0+3*mmsize]
>+    movu        m4, [r2]
>+    movu        m5, [r2+mmsize]
>+    movu        m6, [r2+2*mmsize]
>+    movu        m7, [r2+3*mmsize]
>+    psubw       m0, m4
check r2 or r0 pointer address, if one is aligned, we can combo movu+psubw

>+    psubw       m1, m5
>+    psubw       m2, m6
>+    psubw       m3, m7
>+    lea         r0, [r0+r1]
>+    lea         r2, [r2+r3]
>+    pmaddwd     m0, m0
>+    pmaddwd     m1, m1
>+    pmaddwd     m2, m2
>+    pmaddwd     m3, m3
>+    paddd       m2, m3
>+    paddd       m0, m1
>+    paddd       m0, m2
>+    paddd       m8, m0
>+    dec         r4d
>+    jnz         .loop
extra empty line after JNZ for more readable

>+    mova        m4, m8
>+    pxor        m5, m5
>+    punpckldq   m8, m5
>+    punpckhdq   m4, m5
>+    paddq       m4, m8
>+    movhlps     m5, m4
>+    paddq       m4, m5
>+    paddq       m9, m4
>+    ret
>+
>+%macro SSD_ONE_32 0
>+cglobal pixel_ssd_ss_32x64, 4,7,10
>+    add         r1, r1
>+    add         r3, r3
>+    pxor        m9, m9
>+    xor         r4, r4
>+    call        ssd_ss_32x16
>+    call        ssd_ss_32x16
>+    call        ssd_ss_32x16
>+    call        ssd_ss_32x16
>+    movq        r6, m9
return value in rax, not r6, on Mac OS X, this code will fail.

>+    RET
>+%endmacro
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