[x265] [PATCH] asm: fix sse_pp[32x64] sse2 asm for 12 bit
chen
chenm003 at 163.com
Thu Sep 10 19:28:45 CEST 2015
At 2015-09-10 16:58:52,ramya at multicorewareinc.com wrote:
># HG changeset patch
># User Ramya Sriraman <ramya at multicorewareinc.com>
># Date 1441875518 -19800
># Thu Sep 10 14:28:38 2015 +0530
># Node ID 4b4597b2007f8d4785180e82854678c8a882f30b
># Parent 365f7ed4d89628d49cd6af8d81d4edc01f73ffad
>asm: fix sse_pp[32x64] sse2 asm for 12 bit
>
>diff -r 365f7ed4d896 -r 4b4597b2007f source/common/x86/asm-primitives.cpp
>--- a/source/common/x86/asm-primitives.cpp Tue Sep 08 16:38:01 2015 +0530
>+++ b/source/common/x86/asm-primitives.cpp Thu Sep 10 14:28:38 2015 +0530
>@@ -1001,11 +1001,10 @@
> p.chroma[X265_CSP_I422].cu[BLOCK_422_4x8].sse_pp = (pixel_sse_t)PFX(pixel_ssd_ss_4x8_mmx2);
> p.chroma[X265_CSP_I422].cu[BLOCK_422_8x16].sse_pp = (pixel_sse_t)PFX(pixel_ssd_ss_8x16_sse2);
> p.chroma[X265_CSP_I422].cu[BLOCK_422_16x32].sse_pp = (pixel_sse_t)PFX(pixel_ssd_ss_16x32_sse2);
>-
>+ p.chroma[X265_CSP_I422].cu[BLOCK_422_32x64].sse_pp = (pixel_sse_t)PFX(pixel_ssd_ss_32x64_sse2);
> #if X265_DEPTH <= 10
> p.cu[BLOCK_4x4].sse_ss = PFX(pixel_ssd_ss_4x4_mmx2);
> ALL_LUMA_CU(sse_ss, pixel_ssd_ss, sse2);
>- p.chroma[X265_CSP_I422].cu[BLOCK_422_32x64].sse_pp = (pixel_sse_t)PFX(pixel_ssd_ss_32x64_sse2);
> #endif
>
> p.cu[BLOCK_4x4].dct = PFX(dct4_sse2);
>diff -r 365f7ed4d896 -r 4b4597b2007f source/common/x86/ssd-a.asm
>--- a/source/common/x86/ssd-a.asm Tue Sep 08 16:38:01 2015 +0530
>+++ b/source/common/x86/ssd-a.asm Thu Sep 10 14:28:38 2015 +0530
>@@ -125,6 +125,63 @@
> RET
> %endmacro
>
>+
>+; Function to find ssd for 32x16 block, sse2, 12 bit depth
>+; Defined sepeartely to be called from SSD_ONE_32 macro
>+INIT_XMM sse2
>+cglobal ssd_ss_32x16
>+ pxor m8, m8
>+ mov r4d, 16
>+.loop:
>+ movu m0, [r0]
>+ movu m1, [r0+mmsize]
>+ movu m2, [r0+2*mmsize]
>+ movu m3, [r0+3*mmsize]
>+ movu m4, [r2]
>+ movu m5, [r2+mmsize]
>+ movu m6, [r2+2*mmsize]
>+ movu m7, [r2+3*mmsize]
>+ psubw m0, m4
>+ psubw m1, m5
>+ psubw m2, m6
>+ psubw m3, m7
>+ lea r0, [r0+r1]
>+ lea r2, [r2+r3]
ADD
other code fine
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