[x265] [PATCH 023 of 307] x86: AVX512 pixel_sub_ps_64x64

[mythreyi at multicorewareinc.com]

# HG changeset patch
# User Vignesh Vijayakumar
# Date 1499853711 -19800
#      Wed Jul 12 15:31:51 2017 +0530
# Node ID fda2f079d3358900506a7965569c6a9a39d15eb4
# Parent  c1b7926fb590752578aa8cd17f4b86a7f743791b
x86: AVX512 pixel_sub_ps_64x64

AVX2 performance  : 2.41x
AVX512 performance: 4.33x

diff -r c1b7926fb590 -r fda2f079d335 source/common/x86/asm-primitives.cpp
--- a/source/common/x86/asm-primitives.cpp	Thu Jul 13 11:09:49 2017 +0530
+++ b/source/common/x86/asm-primitives.cpp	Wed Jul 12 15:31:51 2017 +0530
@@ -3810,6 +3810,8 @@
         p.chroma[X265_CSP_I420].cu[BLOCK_420_32x32].add_ps = PFX(pixel_add_ps_32x32_avx2);
         p.chroma[X265_CSP_I422].cu[BLOCK_422_32x64].add_ps = PFX(pixel_add_ps_32x64_avx2);
 
+        p.cu[BLOCK_64x64].sub_ps = PFX(pixel_sub_ps_64x64_avx512);
+
     }
 #endif
 }
diff -r c1b7926fb590 -r fda2f079d335 source/common/x86/pixel-util8.asm
--- a/source/common/x86/pixel-util8.asm	Thu Jul 13 11:09:49 2017 +0530
+++ b/source/common/x86/pixel-util8.asm	Wed Jul 12 15:31:51 2017 +0530
@@ -5782,6 +5782,132 @@
     jnz         .loop
     RET
 %endif
+
+;-----------------------------------------------------------------------------
+; void pixel_sub_ps_64x64(int16_t *dest, intptr_t destride, pixel *src0, pixel *src1, intptr_t srcstride0, intptr_t srcstride1);
+;-----------------------------------------------------------------------------
+%macro PROCESS_SUB_PS_64x8_AVX512 0
+    pmovzxbw    m0,     [r2]
+    pmovzxbw    m1,     [r2 + 32]
+    pmovzxbw    m2,     [r3]
+    pmovzxbw    m3,     [r3 + 32]
+    pmovzxbw    m4,     [r2 + r4]
+    pmovzxbw    m5,     [r2 + r4 + 32]
+    pmovzxbw    m6,     [r3 + r5]
+    pmovzxbw    m7,     [r3 + r5 + 32]
+
+    psubw       m0,     m2
+    psubw       m1,     m3
+    psubw       m4,     m6
+    psubw       m5,     m7
+    movu        [r0],               m0
+    movu        [r0 + 64],          m1
+    movu        [r0 + 2 * r1],      m4
+    movu        [r0 + 2 * r1 + 64], m5
+
+    lea         r0,     [r0 + 4 * r1]
+    lea         r2,     [r2 + 2 * r4]
+    lea         r3,     [r3 + 2 * r5]
+
+    pmovzxbw    m0,     [r2]
+    pmovzxbw    m1,     [r2 + 32]
+    pmovzxbw    m2,     [r3]
+    pmovzxbw    m3,     [r3 + 32]
+    pmovzxbw    m4,     [r2 + r4]
+    pmovzxbw    m5,     [r2 + r4 + 32]
+    pmovzxbw    m6,     [r3 + r5]
+    pmovzxbw    m7,     [r3 + r5 + 32]
+
+    psubw       m0,     m2
+    psubw       m1,     m3
+    psubw       m4,     m6
+    psubw       m5,     m7
+    movu        [r0],               m0
+    movu        [r0 + 64],          m1
+    movu        [r0 + 2 * r1],      m4
+    movu        [r0 + 2 * r1 + 64], m5
+
+    lea         r0,     [r0 + 4 * r1]
+    lea         r2,     [r2 + 2 * r4]
+    lea         r3,     [r3 + 2 * r5]
+
+    pmovzxbw    m0,     [r2]
+    pmovzxbw    m1,     [r2 + 32]
+    pmovzxbw    m2,     [r3]
+    pmovzxbw    m3,     [r3 + 32]
+    pmovzxbw    m4,     [r2 + r4]
+    pmovzxbw    m5,     [r2 + r4 + 32]
+    pmovzxbw    m6,     [r3 + r5]
+    pmovzxbw    m7,     [r3 + r5 + 32]
+
+    psubw       m0,     m2
+    psubw       m1,     m3
+    psubw       m4,     m6
+    psubw       m5,     m7
+    movu        [r0],               m0
+    movu        [r0 + 64],          m1
+    movu        [r0 + 2 * r1],      m4
+    movu        [r0 + 2 * r1 + 64], m5
+
+    lea         r0,     [r0 + 4 * r1]
+    lea         r2,     [r2 + 2 * r4]
+    lea         r3,     [r3 + 2 * r5]
+
+    pmovzxbw    m0,     [r2]
+    pmovzxbw    m1,     [r2 + 32]
+    pmovzxbw    m2,     [r3]
+    pmovzxbw    m3,     [r3 + 32]
+    pmovzxbw    m4,     [r2 + r4]
+    pmovzxbw    m5,     [r2 + r4 + 32]
+    pmovzxbw    m6,     [r3 + r5]
+    pmovzxbw    m7,     [r3 + r5 + 32]
+
+    psubw       m0,     m2
+    psubw       m1,     m3
+    psubw       m4,     m6
+    psubw       m5,     m7
+    movu        [r0],               m0
+    movu        [r0 + 64],          m1
+    movu        [r0 + 2 * r1],      m4
+    movu        [r0 + 2 * r1 + 64], m5
+%endmacro
+
+%if HIGH_BIT_DEPTH==0
+%if ARCH_X86_64
+INIT_ZMM avx512
+cglobal pixel_sub_ps_64x64, 6, 7, 8
+    PROCESS_SUB_PS_64x8_AVX512
+    lea         r0,     [r0 + 4 * r1]
+    lea         r2,     [r2 + 2 * r4]
+    lea         r3,     [r3 + 2 * r5]
+    PROCESS_SUB_PS_64x8_AVX512
+    lea         r0,     [r0 + 4 * r1]
+    lea         r2,     [r2 + 2 * r4]
+    lea         r3,     [r3 + 2 * r5]
+    PROCESS_SUB_PS_64x8_AVX512
+    lea         r0,     [r0 + 4 * r1]
+    lea         r2,     [r2 + 2 * r4]
+    lea         r3,     [r3 + 2 * r5]
+    PROCESS_SUB_PS_64x8_AVX512
+    lea         r0,     [r0 + 4 * r1]
+    lea         r2,     [r2 + 2 * r4]
+    lea         r3,     [r3 + 2 * r5]
+    PROCESS_SUB_PS_64x8_AVX512
+    lea         r0,     [r0 + 4 * r1]
+    lea         r2,     [r2 + 2 * r4]
+    lea         r3,     [r3 + 2 * r5]
+    PROCESS_SUB_PS_64x8_AVX512
+    lea         r0,     [r0 + 4 * r1]
+    lea         r2,     [r2 + 2 * r4]
+    lea         r3,     [r3 + 2 * r5]
+    PROCESS_SUB_PS_64x8_AVX512
+    lea         r0,     [r0 + 4 * r1]
+    lea         r2,     [r2 + 2 * r4]
+    lea         r3,     [r3 + 2 * r5]
+    PROCESS_SUB_PS_64x8_AVX512
+    RET
+%endif
+%endif
 ;=============================================================================
 ; variance
 ;=============================================================================