[x265] [PATCH 140 of 307] x86: AVX512 interp_4tap_horiz_ps_32xN for high bit depth
mythreyi at multicorewareinc.com
mythreyi at multicorewareinc.com
Sat Apr 7 04:32:18 CEST 2018
# HG changeset patch
# User Jayashri Murugan <jayashri at multicorewareinc.com>
# Date 1505725417 -19800
# Mon Sep 18 14:33:37 2017 +0530
# Node ID 2ac4332dafdc149be93872768cb233923c7edcab
# Parent 94a80faedde6b0510c58d80c812170c120d8d918
x86: AVX512 interp_4tap_horiz_ps_32xN for high bit depth
i420
Size | AVX2 performance | AVX512 performance
----------------------------------------------
32x8 | 13.58x | 40.28x
32x16 | 14.32x | 42.30x
32x24 | 14.46x | 40.00x
32x32 | 14.50x | 41.34x
i422
Size | AVX2 performance | AVX512 performance
----------------------------------------------
32x16 | 14.38x | 42.33x
32x32 | 14.50x | 41.27x
32x48 | 14.60x | 42.48x
32x64 | 14.60x | 43.20x
i444
Size | AVX2 performance | AVX512 performance
----------------------------------------------
32x8 | 13.85x | 39.39x
32x16 | 14.34x | 42.21x
32x24 | 14.46x | 40.33x
32x32 | 14.49x | 41.47x
32x64 | 14.42x | 43.05x
diff -r 94a80faedde6 -r 2ac4332dafdc source/common/x86/asm-primitives.cpp
--- a/source/common/x86/asm-primitives.cpp Wed Nov 01 15:08:04 2017 +0530
+++ b/source/common/x86/asm-primitives.cpp Mon Sep 18 14:33:37 2017 +0530
@@ -2655,7 +2655,21 @@
p.cu[BLOCK_8x8].dct = PFX(dct8_avx512);
-
+ p.chroma[X265_CSP_I420].pu[CHROMA_420_32x32].filter_hps = PFX(interp_4tap_horiz_ps_32x32_avx512);
+ p.chroma[X265_CSP_I420].pu[CHROMA_420_32x16].filter_hps = PFX(interp_4tap_horiz_ps_32x16_avx512);
+ p.chroma[X265_CSP_I420].pu[CHROMA_420_32x24].filter_hps = PFX(interp_4tap_horiz_ps_32x24_avx512);
+ p.chroma[X265_CSP_I420].pu[CHROMA_420_32x8].filter_hps = PFX(interp_4tap_horiz_ps_32x8_avx512);
+
+ p.chroma[X265_CSP_I422].pu[CHROMA_422_32x64].filter_hps = PFX(interp_4tap_horiz_ps_32x64_avx512);
+ p.chroma[X265_CSP_I422].pu[CHROMA_422_32x32].filter_hps = PFX(interp_4tap_horiz_ps_32x32_avx512);
+ p.chroma[X265_CSP_I422].pu[CHROMA_422_32x48].filter_hps = PFX(interp_4tap_horiz_ps_32x48_avx512);
+ p.chroma[X265_CSP_I422].pu[CHROMA_422_32x16].filter_hps = PFX(interp_4tap_horiz_ps_32x16_avx512);
+
+ p.chroma[X265_CSP_I444].pu[LUMA_32x32].filter_hps = PFX(interp_4tap_horiz_ps_32x32_avx512);
+ p.chroma[X265_CSP_I444].pu[LUMA_32x16].filter_hps = PFX(interp_4tap_horiz_ps_32x16_avx512);
+ p.chroma[X265_CSP_I444].pu[LUMA_32x64].filter_hps = PFX(interp_4tap_horiz_ps_32x64_avx512);
+ p.chroma[X265_CSP_I444].pu[LUMA_32x24].filter_hps = PFX(interp_4tap_horiz_ps_32x24_avx512);
+ p.chroma[X265_CSP_I444].pu[LUMA_32x8].filter_hps = PFX(interp_4tap_horiz_ps_32x8_avx512);
}
#endif
diff -r 94a80faedde6 -r 2ac4332dafdc source/common/x86/ipfilter16.asm
--- a/source/common/x86/ipfilter16.asm Wed Nov 01 15:08:04 2017 +0530
+++ b/source/common/x86/ipfilter16.asm Mon Sep 18 14:33:37 2017 +0530
@@ -6115,6 +6115,135 @@
FILTER_VER_PP_CHROMA_64xN_AVX512 48
FILTER_VER_PP_CHROMA_64xN_AVX512 64
%endif
+
+%macro PROCESS_IPFILTER_CHROMA_PS_32x2_AVX512 0
+ ; register map
+ ; m0 , m1 - interpolate coeff
+ ; m2 , m3 - shuffle load order table
+ ; m4 - INTERP_OFFSET_PS
+ ; m5 - shuffle store order table
+
+ movu m6, [r0]
+ movu m7, [r0 + 8]
+
+ pshufb m8, m6, m3
+ pshufb m6, m2
+ pmaddwd m6, m0
+ pmaddwd m8, m1
+ paddd m6, m8
+ paddd m6, m4
+ psrad m6, INTERP_SHIFT_PS
+
+ pshufb m8, m7, m3
+ pshufb m7, m2
+ pmaddwd m7, m0
+ pmaddwd m8, m1
+ paddd m7, m8
+ paddd m7, m4
+ psrad m7, INTERP_SHIFT_PS
+
+ packssdw m6, m7
+ pshufb m6, m5
+ movu [r2], m6
+
+ movu m6, [r0 + r1]
+ movu m7, [r0 + r1 + 8]
+
+ pshufb m8, m6, m3
+ pshufb m6, m2
+ pmaddwd m6, m0
+ pmaddwd m8, m1
+ paddd m6, m8
+ paddd m6, m4
+ psrad m6, INTERP_SHIFT_PS
+
+ pshufb m8, m7, m3
+ pshufb m7, m2
+ pmaddwd m7, m0
+ pmaddwd m8, m1
+ paddd m7, m8
+ paddd m7, m4
+ psrad m7, INTERP_SHIFT_PS
+
+ packssdw m6, m7
+ pshufb m6, m5
+ movu [r2 + r3], m6
+%endmacro
+
+%macro PROCESS_IPFILTER_CHROMA_PS_32x1_AVX512 0
+ movu m6, [r0]
+ movu m7, [r0 + 8]
+
+ pshufb m8, m6, m3
+ pshufb m6, m2
+ pmaddwd m6, m0
+ pmaddwd m8, m1
+ paddd m6, m8
+ paddd m6, m4
+ psrad m6, INTERP_SHIFT_PS
+
+ pshufb m8, m7, m3
+ pshufb m7, m2
+ pmaddwd m7, m0
+ pmaddwd m8, m1
+ paddd m7, m8
+ paddd m7, m4
+ psrad m7, INTERP_SHIFT_PS
+
+ packssdw m6, m7
+ pshufb m6, m5
+ movu [r2], m6
+%endmacro
+
+INIT_ZMM avx512
+%if ARCH_X86_64 == 1
+%macro IPFILTER_CHROMA_PS_AVX512_32xN 1
+cglobal interp_4tap_horiz_ps_32x%1, 4,7,9
+ add r1d, r1d
+ add r3d, r3d
+ mov r4d, r4m
+ mov r5d, r5m
+%ifdef PIC
+ lea r6, [tab_ChromaCoeff]
+ vpbroadcastd m0, [r6 + r4 * 8]
+ vpbroadcastd m1, [r6 + r4 * 8 + 4]
+%else
+ vpbroadcastd m0, [tab_ChromaCoeff + r4 * 8]
+ vpbroadcastd m1, [tab_ChromaCoeff + r4 * 8 + 4]
+%endif
+ vbroadcasti32x8 m2, [interp8_hpp_shuf1_load_avx512]
+ vbroadcasti32x8 m3, [interp8_hpp_shuf2_load_avx512]
+ vbroadcasti32x4 m4, [INTERP_OFFSET_PS]
+ vbroadcasti32x8 m5, [interp8_hpp_shuf1_store_avx512]
+
+ mov r6d, %1
+ sub r0, 2
+ test r5d, r5d
+ jz .loop
+ sub r0, r1
+ add r6d, 3
+ PROCESS_IPFILTER_CHROMA_PS_32x1_AVX512
+ lea r0, [r0 + r1]
+ lea r2, [r2 + r3]
+ dec r6d
+
+.loop:
+ PROCESS_IPFILTER_CHROMA_PS_32x2_AVX512
+ lea r0, [r0 + 2 * r1]
+ lea r2, [r2 + 2 * r3]
+ sub r6d, 2
+ jnz .loop
+ RET
+%endmacro
+%endif
+
+IPFILTER_CHROMA_PS_AVX512_32xN 8
+IPFILTER_CHROMA_PS_AVX512_32xN 16
+IPFILTER_CHROMA_PS_AVX512_32xN 24
+IPFILTER_CHROMA_PS_AVX512_32xN 32
+IPFILTER_CHROMA_PS_AVX512_32xN 48
+IPFILTER_CHROMA_PS_AVX512_32xN 64
+
;-------------------------------------------------------------------------------------------------------------
;ipfilter_chroma_avx512 code end
;-------------------------------------------------------------------------------------------------------------
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