[x265] [PATCH 151 of 307] x86: AVX512 interp_4tap_vert_ps_64xN for high bit depth
mythreyi at multicorewareinc.com
mythreyi at multicorewareinc.com
Sat Apr 7 04:32:29 CEST 2018
# HG changeset patch
# User Vignesh Vijayakumar<vignesh at multicorewareinc.com>
# Date 1510030534 -19800
# Tue Nov 07 10:25:34 2017 +0530
# Node ID 5517caaeb88b0f76a78706a867a4fa24fb17f64e
# Parent c983858deccb26e5b4c957fbff959c1e74f84756
x86: AVX512 interp_4tap_vert_ps_64xN for high bit depth
i444
Size | AVX2 performance | AVX512 performance
----------------------------------------------
64x16 | 27.45x | 42.45x
64x32 | 27.77x | 43.65x
64x48 | 28.06x | 43.04x
64x64 | 28.18x | 43.34x
diff -r c983858deccb -r 5517caaeb88b source/common/x86/asm-primitives.cpp
--- a/source/common/x86/asm-primitives.cpp Tue Nov 07 10:06:23 2017 +0530
+++ b/source/common/x86/asm-primitives.cpp Tue Nov 07 10:25:34 2017 +0530
@@ -2639,6 +2639,10 @@
p.chroma[X265_CSP_I444].pu[LUMA_64x32].filter_vpp = PFX(interp_4tap_vert_pp_64x32_avx512);
p.chroma[X265_CSP_I444].pu[LUMA_64x48].filter_vpp = PFX(interp_4tap_vert_pp_64x48_avx512);
p.chroma[X265_CSP_I444].pu[LUMA_64x64].filter_vpp = PFX(interp_4tap_vert_pp_64x64_avx512);
+ p.chroma[X265_CSP_I444].pu[LUMA_64x16].filter_vps = PFX(interp_4tap_vert_ps_64x16_avx512);
+ p.chroma[X265_CSP_I444].pu[LUMA_64x32].filter_vps = PFX(interp_4tap_vert_ps_64x32_avx512);
+ p.chroma[X265_CSP_I444].pu[LUMA_64x48].filter_vps = PFX(interp_4tap_vert_ps_64x48_avx512);
+ p.chroma[X265_CSP_I444].pu[LUMA_64x64].filter_vps = PFX(interp_4tap_vert_ps_64x64_avx512);
p.chroma[X265_CSP_I444].pu[LUMA_48x64].filter_vpp = PFX(interp_4tap_vert_pp_48x64_avx512);
p.chroma[X265_CSP_I444].pu[LUMA_32x8].filter_vpp = PFX(interp_4tap_vert_pp_32x8_avx512);
p.chroma[X265_CSP_I444].pu[LUMA_32x16].filter_vpp = PFX(interp_4tap_vert_pp_32x16_avx512);
diff -r c983858deccb -r 5517caaeb88b source/common/x86/ipfilter16.asm
--- a/source/common/x86/ipfilter16.asm Tue Nov 07 10:06:23 2017 +0530
+++ b/source/common/x86/ipfilter16.asm Tue Nov 07 10:25:34 2017 +0530
@@ -7423,6 +7423,128 @@
FILTER_VER_PS_CHROMA_32xN_AVX512 48
FILTER_VER_PS_CHROMA_32xN_AVX512 64
%endif
+
+%macro PROCESS_CHROMA_VERT_PS_64x2_AVX512 0
+ movu m1, [r0]
+ movu m3, [r0 + r1]
+ punpcklwd m0, m1, m3
+ pmaddwd m0, [r5]
+ punpckhwd m1, m3
+ pmaddwd m1, [r5]
+
+ movu m9, [r0 + mmsize]
+ movu m11, [r0 + r1 + mmsize]
+ punpcklwd m8, m9, m11
+ pmaddwd m8, [r5]
+ punpckhwd m9, m11
+ pmaddwd m9, [r5]
+
+ movu m4, [r0 + 2 * r1]
+ punpcklwd m2, m3, m4
+ pmaddwd m2, [r5]
+ punpckhwd m3, m4
+ pmaddwd m3, [r5]
+
+ movu m12, [r0 + 2 * r1 + mmsize]
+ punpcklwd m10, m11, m12
+ pmaddwd m10, [r5]
+ punpckhwd m11, m12
+ pmaddwd m11, [r5]
+
+ lea r0, [r0 + 2 * r1]
+ movu m5, [r0 + r1]
+ punpcklwd m6, m4, m5
+ pmaddwd m6, [r5 + 1 * mmsize]
+ paddd m0, m6
+ punpckhwd m4, m5
+ pmaddwd m4, [r5 + 1 * mmsize]
+ paddd m1, m4
+
+ movu m13, [r0 + r1 + mmsize]
+ punpcklwd m14, m12, m13
+ pmaddwd m14, [r5 + 1 * mmsize]
+ paddd m8, m14
+ punpckhwd m12, m13
+ pmaddwd m12, [r5 + 1 * mmsize]
+ paddd m9, m12
+
+ movu m4, [r0 + 2 * r1]
+ punpcklwd m6, m5, m4
+ pmaddwd m6, [r5 + 1 * mmsize]
+ paddd m2, m6
+ punpckhwd m5, m4
+ pmaddwd m5, [r5 + 1 * mmsize]
+ paddd m3, m5
+
+ movu m12, [r0 + 2 * r1 + mmsize]
+ punpcklwd m14, m13, m12
+ pmaddwd m14, [r5 + 1 * mmsize]
+ paddd m10, m14
+ punpckhwd m13, m12
+ pmaddwd m13, [r5 + 1 * mmsize]
+ paddd m11, m13
+
+ paddd m0, m7
+ paddd m1, m7
+ paddd m2, m7
+ paddd m3, m7
+ paddd m8, m7
+ paddd m9, m7
+ paddd m10, m7
+ paddd m11, m7
+
+ psrad m0, INTERP_SHIFT_PS
+ psrad m1, INTERP_SHIFT_PS
+ psrad m2, INTERP_SHIFT_PS
+ psrad m3, INTERP_SHIFT_PS
+ psrad m8, INTERP_SHIFT_PS
+ psrad m9, INTERP_SHIFT_PS
+ psrad m10, INTERP_SHIFT_PS
+ psrad m11, INTERP_SHIFT_PS
+
+ packssdw m0, m1
+ packssdw m2, m3
+ packssdw m8, m9
+ packssdw m10, m11
+ movu [r2], m0
+ movu [r2 + r3], m2
+ movu [r2 + mmsize], m8
+ movu [r2 + r3 + mmsize], m10
+%endmacro
+
+;-----------------------------------------------------------------------------------------------------------------
+; void interp_4tap_vert(int16_t *src, intptr_t srcStride, int16_t *dst, intptr_t dstStride, int coeffIdx)
+;-----------------------------------------------------------------------------------------------------------------
+%macro FILTER_VER_PS_CHROMA_64xN_AVX512 1
+INIT_ZMM avx512
+cglobal interp_4tap_vert_ps_64x%1, 5, 7, 15
+ add r1d, r1d
+ add r3d, r3d
+ sub r0, r1
+ shl r4d, 7
+
+%ifdef PIC
+ lea r5, [tab_ChromaCoeffV_avx512]
+ lea r5, [r5 + r4]
+%else
+ lea r5, [tab_ChromaCoeffV_avx512 + r4]
+%endif
+ vbroadcasti32x4 m7, [INTERP_OFFSET_PS]
+
+%rep %1/2 - 1
+ PROCESS_CHROMA_VERT_PS_64x2_AVX512
+ lea r2, [r2 + 2 * r3]
+%endrep
+ PROCESS_CHROMA_VERT_PS_64x2_AVX512
+ RET
+%endmacro
+
+%if ARCH_X86_64
+FILTER_VER_PS_CHROMA_64xN_AVX512 16
+FILTER_VER_PS_CHROMA_64xN_AVX512 32
+FILTER_VER_PS_CHROMA_64xN_AVX512 48
+FILTER_VER_PS_CHROMA_64xN_AVX512 64
+%endif
;-------------------------------------------------------------------------------------------------------------
;ipfilter_chroma_avx512 code end
;-------------------------------------------------------------------------------------------------------------
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