[x265] [PATCH 192 of 307] x86: AVX512 interp_8tap_vert_sp_16xN and interp_8tap_vert_ss_16xN
mythreyi at multicorewareinc.com
mythreyi at multicorewareinc.com
Sat Apr 7 04:33:10 CEST 2018
# HG changeset patch
# User Vignesh Vijayakumar<vignesh at multicorewareinc.com>
# Date 1511433052 -19800
# Thu Nov 23 16:00:52 2017 +0530
# Node ID 66679e6701cf73584ec0db224927ee9eb24893a7
# Parent b7ebc01ecbfe2510fbe6a2ce305bdb479267decf
x86: AVX512 interp_8tap_vert_sp_16xN and interp_8tap_vert_ss_16xN
luma_vsp
Size | AVX2 performance | AVX512 performance
----------------------------------------------
16x4 | 9.68x | 16.85x
16x8 | 11.69x | 18.47x
16x12 | 13.43x | 18.34x
16x16 | 13.26x | 18.96x
16x32 | 12.96x | 19.66x
16x64 | 13.12x | 19.72x
luma_vss
Size | AVX2 performance | AVX512 performance
----------------------------------------------
16x4 | 7.90x | 15.87x
16x8 | 8.58x | 15.10x
16x12 | 10.78x | 15.38x
16x16 | 11.51x | 16.27x
16x32 | 11.92x | 16.93x
16x64 | 10.17x | 17.24x
diff -r b7ebc01ecbfe -r 66679e6701cf source/common/x86/asm-primitives.cpp
--- a/source/common/x86/asm-primitives.cpp Thu Nov 23 13:52:24 2017 +0530
+++ b/source/common/x86/asm-primitives.cpp Thu Nov 23 16:00:52 2017 +0530
@@ -2835,6 +2835,12 @@
p.chroma[X265_CSP_I422].pu[CHROMA_422_24x64].filter_vsp = PFX(interp_4tap_vert_sp_24x64_avx512);
p.chroma[X265_CSP_I444].pu[LUMA_24x32].filter_vsp = PFX(interp_4tap_vert_sp_24x32_avx512);
+ p.pu[LUMA_16x4].luma_vss = PFX(interp_8tap_vert_ss_16x4_avx512);
+ p.pu[LUMA_16x8].luma_vss = PFX(interp_8tap_vert_ss_16x8_avx512);
+ p.pu[LUMA_16x12].luma_vss = PFX(interp_8tap_vert_ss_16x12_avx512);
+ p.pu[LUMA_16x16].luma_vss = PFX(interp_8tap_vert_ss_16x16_avx512);
+ p.pu[LUMA_16x32].luma_vss = PFX(interp_8tap_vert_ss_16x32_avx512);
+ p.pu[LUMA_16x64].luma_vss = PFX(interp_8tap_vert_ss_16x64_avx512);
p.pu[LUMA_32x8].luma_vss = PFX(interp_8tap_vert_ss_32x8_avx512);
p.pu[LUMA_32x16].luma_vss = PFX(interp_8tap_vert_ss_32x16_avx512);
p.pu[LUMA_32x32].luma_vss = PFX(interp_8tap_vert_ss_32x32_avx512);
@@ -2845,6 +2851,12 @@
p.pu[LUMA_64x48].luma_vss = PFX(interp_8tap_vert_ss_64x48_avx512);
p.pu[LUMA_64x64].luma_vss = PFX(interp_8tap_vert_ss_64x64_avx512);
+ p.pu[LUMA_16x4].luma_vsp = PFX(interp_8tap_vert_sp_16x4_avx512);
+ p.pu[LUMA_16x8].luma_vsp = PFX(interp_8tap_vert_sp_16x8_avx512);
+ p.pu[LUMA_16x12].luma_vsp = PFX(interp_8tap_vert_sp_16x12_avx512);
+ p.pu[LUMA_16x16].luma_vsp = PFX(interp_8tap_vert_sp_16x16_avx512);
+ p.pu[LUMA_16x32].luma_vsp = PFX(interp_8tap_vert_sp_16x32_avx512);
+ p.pu[LUMA_16x64].luma_vsp = PFX(interp_8tap_vert_sp_16x64_avx512);
p.pu[LUMA_32x8].luma_vsp = PFX(interp_8tap_vert_sp_32x8_avx512);
p.pu[LUMA_32x16].luma_vsp = PFX(interp_8tap_vert_sp_32x16_avx512);
p.pu[LUMA_32x32].luma_vsp = PFX(interp_8tap_vert_sp_32x32_avx512);
diff -r b7ebc01ecbfe -r 66679e6701cf source/common/x86/ipfilter16.asm
--- a/source/common/x86/ipfilter16.asm Thu Nov 23 13:52:24 2017 +0530
+++ b/source/common/x86/ipfilter16.asm Thu Nov 23 16:00:52 2017 +0530
@@ -10795,6 +10795,166 @@
;-------------------------------------------------------------------------------------------------------------
;avx512 luma_vss and luma_vsp code start
;-------------------------------------------------------------------------------------------------------------
+%macro PROCESS_LUMA_VERT_S_16x4_AVX512 1
+ movu ym1, [r0]
+ movu ym3, [r0 + r1]
+ vinserti32x8 m1, [r0 + 2 * r1], 1
+ vinserti32x8 m3, [r0 + r7], 1
+ punpcklwd m0, m1, m3
+ pmaddwd m0, m15
+ punpckhwd m1, m3
+ pmaddwd m1, m15
+
+ lea r6, [r0 + 4 * r1]
+ movu ym4, [r0 + 2 * r1]
+ vinserti32x8 m4, [r6], 1
+ punpcklwd m2, m3, m4
+ pmaddwd m2, m15
+ punpckhwd m3, m4
+ pmaddwd m3, m15
+
+ movu ym5, [r0 + r7]
+ vinserti32x8 m5, [r6 + r1], 1
+ punpcklwd m6, m4, m5
+ pmaddwd m6, m16
+ punpckhwd m4, m5
+ pmaddwd m4, m16
+
+ paddd m0, m6
+ paddd m1, m4
+
+ movu ym4, [r6]
+ vinserti32x8 m4, [r6 + 2 * r1], 1
+ punpcklwd m6, m5, m4
+ pmaddwd m6, m16
+ punpckhwd m5, m4
+ pmaddwd m5, m16
+
+ paddd m2, m6
+ paddd m3, m5
+
+ movu ym11, [r6 + r1]
+ vinserti32x8 m11, [r6 + r7], 1
+ punpcklwd m8, m4, m11
+ pmaddwd m8, m17
+ punpckhwd m4, m11
+ pmaddwd m4, m17
+
+ movu ym12, [r6 + 2 * r1]
+ vinserti32x8 m12, [r6 + 4 * r1], 1
+ punpcklwd m10, m11, m12
+ pmaddwd m10, m17
+ punpckhwd m11, m12
+ pmaddwd m11, m17
+
+ lea r4, [r6 + 4 * r1]
+ movu ym13, [r6 + r7]
+ vinserti32x8 m13, [r4 + r1], 1
+ punpcklwd m14, m12, m13
+ pmaddwd m14, m18
+ punpckhwd m12, m13
+ pmaddwd m12, m18
+
+ paddd m8, m14
+ paddd m4, m12
+ paddd m0, m8
+ paddd m1, m4
+
+ movu ym12, [r6 + 4 * r1]
+ vinserti32x8 m12, [r4 + 2 * r1], 1
+ punpcklwd m14, m13, m12
+ pmaddwd m14, m18
+ punpckhwd m13, m12
+ pmaddwd m13, m18
+
+ paddd m10, m14
+ paddd m11, m13
+ paddd m2, m10
+ paddd m3, m11
+
+%ifidn %1, sp
+ paddd m0, m19
+ paddd m1, m19
+ paddd m2, m19
+ paddd m3, m19
+
+ psrad m0, INTERP_SHIFT_SP
+ psrad m1, INTERP_SHIFT_SP
+ psrad m2, INTERP_SHIFT_SP
+ psrad m3, INTERP_SHIFT_SP
+
+ packssdw m0, m1
+ packssdw m2, m3
+ CLIPW2 m0, m2, m20, m21
+%else
+ psrad m0, 6
+ psrad m1, 6
+ psrad m2, 6
+ psrad m3, 6
+
+ packssdw m0, m1
+ packssdw m2, m3
+%endif
+
+ movu [r2], ym0
+ movu [r2 + r3], ym2
+ vextracti32x8 [r2 + 2 * r3], m0, 1
+ vextracti32x8 [r2 + r5], m2, 1
+%endmacro
+;-----------------------------------------------------------------------------------------------------------------
+; void interp_8tap_vert(int16_t *src, intptr_t srcStride, int16_t *dst, intptr_t dstStride, int coeffIdx)
+;-----------------------------------------------------------------------------------------------------------------
+%macro FILTER_VER_S_LUMA_16xN_AVX512 2
+INIT_ZMM avx512
+cglobal interp_8tap_vert_%1_16x%2, 5, 8, 22
+ add r1d, r1d
+ add r3d, r3d
+ lea r7, [3 * r1]
+ sub r0, r7
+ shl r4d, 8
+%ifdef PIC
+ lea r5, [tab_LumaCoeffVer_avx512]
+ mova m15, [r5 + r4]
+ mova m16, [r5 + r4 + 1 * mmsize]
+ mova m17, [r5 + r4 + 2 * mmsize]
+ mova m18, [r5 + r4 + 3 * mmsize]
+%else
+ lea r5, [tab_LumaCoeffVer_avx512 + r4]
+ mova m15, [r5]
+ mova m16, [r5 + 1 * mmsize]
+ mova m17, [r5 + 2 * mmsize]
+ mova m18, [r5 + 3 * mmsize]
+%endif
+%ifidn %1, sp
+ vbroadcasti32x4 m19, [INTERP_OFFSET_SP]
+ pxor m20, m20
+ vbroadcasti32x8 m21, [pw_pixel_max]
+%endif
+ lea r5, [3 * r3]
+%rep %2/4 - 1
+ PROCESS_LUMA_VERT_S_16x4_AVX512 %1
+ lea r0, [r0 + 4 * r1]
+ lea r2, [r2 + 4 * r3]
+%endrep
+ PROCESS_LUMA_VERT_S_16x4_AVX512 %1
+ RET
+%endmacro
+
+%if ARCH_X86_64
+ FILTER_VER_S_LUMA_16xN_AVX512 ss, 4
+ FILTER_VER_S_LUMA_16xN_AVX512 ss, 8
+ FILTER_VER_S_LUMA_16xN_AVX512 ss, 12
+ FILTER_VER_S_LUMA_16xN_AVX512 ss, 16
+ FILTER_VER_S_LUMA_16xN_AVX512 ss, 32
+ FILTER_VER_S_LUMA_16xN_AVX512 ss, 64
+ FILTER_VER_S_LUMA_16xN_AVX512 sp, 4
+ FILTER_VER_S_LUMA_16xN_AVX512 sp, 8
+ FILTER_VER_S_LUMA_16xN_AVX512 sp, 12
+ FILTER_VER_S_LUMA_16xN_AVX512 sp, 16
+ FILTER_VER_S_LUMA_16xN_AVX512 sp, 32
+ FILTER_VER_S_LUMA_16xN_AVX512 sp, 64
+%endif
+
%macro PROCESS_LUMA_VERT_S_32x2_AVX512 1
movu m1, [r0] ;0 row
movu m3, [r0 + r1] ;1 row
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