[x265] [PATCH 196 of 307] x86: AVX512 interp_8tap_horiz_ps_16xN for high bit depth
mythreyi at multicorewareinc.com
mythreyi at multicorewareinc.com
Sat Apr 7 04:33:14 CEST 2018
# HG changeset patch
# User Jayashri Murugan <jayashri at multicorewareinc.com>
# Date 1511427002 -19800
# Thu Nov 23 14:20:02 2017 +0530
# Node ID 360960bc701dcc51e491699fc3a4a9cffc4e627f
# Parent 47b99c09008b1921881b0dfa00d80cce1f8d15eb
x86: AVX512 interp_8tap_horiz_ps_16xN for high bit depth
Size | AVX2 performance | AVX512 performance
----------------------------------------------
16x4 | 7.19x | 18.08x
16x8 | 7.93x | 15.84x
16x12 | 8.07x | 15.80x
16x16 | 7.17x | 19.46x
16x32 | 7.33x | 18.68x
16x64 | 8.52x | 17.27x
diff -r 47b99c09008b -r 360960bc701d source/common/x86/asm-primitives.cpp
--- a/source/common/x86/asm-primitives.cpp Fri Nov 24 12:09:05 2017 +0530
+++ b/source/common/x86/asm-primitives.cpp Thu Nov 23 14:20:02 2017 +0530
@@ -2957,7 +2957,13 @@
p.pu[LUMA_64x32].luma_hps = PFX(interp_8tap_horiz_ps_64x32_avx512);
p.pu[LUMA_64x48].luma_hps = PFX(interp_8tap_horiz_ps_64x48_avx512);
p.pu[LUMA_64x64].luma_hps = PFX(interp_8tap_horiz_ps_64x64_avx512);
-
+ //Luma_hps_16xN
+ p.pu[LUMA_16x4].luma_hps = PFX(interp_8tap_horiz_ps_16x4_avx512);
+ p.pu[LUMA_16x8].luma_hps = PFX(interp_8tap_horiz_ps_16x8_avx512);
+ p.pu[LUMA_16x12].luma_hps = PFX(interp_8tap_horiz_ps_16x12_avx512);
+ p.pu[LUMA_16x16].luma_hps = PFX(interp_8tap_horiz_ps_16x16_avx512);
+ p.pu[LUMA_16x32].luma_hps = PFX(interp_8tap_horiz_ps_16x32_avx512);
+ p.pu[LUMA_16x64].luma_hps = PFX(interp_8tap_horiz_ps_16x64_avx512);
}
#endif
diff -r 47b99c09008b -r 360960bc701d source/common/x86/ipfilter16.asm
--- a/source/common/x86/ipfilter16.asm Fri Nov 24 12:09:05 2017 +0530
+++ b/source/common/x86/ipfilter16.asm Thu Nov 23 14:20:02 2017 +0530
@@ -10789,6 +10789,227 @@
IPFILTER_LUMA_PS_AVX512_64xN 64
%endif
+%macro PROCESS_IPFILTER_LUMA_PS_16x4_AVX512 0
+ ; register map
+ ; m0, m1, m2, m3 - interpolate coeff
+ ; m4, m5 - shuffle load order table
+ ; m6 - INTERP_OFFSET_PS
+ ; m7 - shuffle store order table
+
+ movu ym8, [r0]
+ vinserti32x8 m8, [r0 + r1], 1
+ movu ym9, [r0 + 8]
+ vinserti32x8 m9, [r0 + r1 + 8], 1
+ movu ym10, [r0 + 16]
+ vinserti32x8 m10, [r0 + r1 + 16], 1
+
+ pshufb m11, m8, m5
+ pshufb m8, m4
+ pshufb m12, m9, m5
+ pshufb m9, m4
+ pshufb m13, m10, m5
+ pshufb m10, m4
+
+ pmaddwd m8, m0
+ pmaddwd m11, m1
+ paddd m8, m11
+ pmaddwd m11, m12, m3
+ pmaddwd m14, m9, m2
+ paddd m11, m14
+ paddd m8, m11
+ paddd m8, m6
+ psrad m8, INTERP_SHIFT_PS
+
+ pmaddwd m9, m0
+ pmaddwd m12, m1
+ paddd m9, m12
+ pmaddwd m13, m3
+ pmaddwd m10, m2
+ paddd m10, m13
+ paddd m9, m10
+ paddd m9, m6
+ psrad m9, INTERP_SHIFT_PS
+
+ packssdw m8, m9
+ pshufb m8, m7
+ movu [r2], ym8
+ vextracti32x8 [r2 + r3],m8, 1
+
+ movu ym8, [r0 + 2 * r1]
+ vinserti32x8 m8, [r0 + r6], 1
+ movu ym9, [r0 + 2 * r1 + 8]
+ vinserti32x8 m9, [r0 + r6 + 8], 1
+ movu ym10, [r0 + 2 * r1 + 16]
+ vinserti32x8 m10, [r0 + r6 + 16], 1
+
+ pshufb m11, m8, m5
+ pshufb m8, m4
+ pshufb m12, m9, m5
+ pshufb m9, m4
+ pshufb m13, m10, m5
+ pshufb m10, m4
+
+ pmaddwd m8, m0
+ pmaddwd m11, m1
+ paddd m8, m11
+ pmaddwd m11, m12, m3
+ pmaddwd m14, m9, m2
+ paddd m11, m14
+ paddd m8, m11
+ paddd m8, m6
+ psrad m8, INTERP_SHIFT_PS
+
+ pmaddwd m9, m0
+ pmaddwd m12, m1
+ paddd m9, m12
+ pmaddwd m12, m13, m3
+ pmaddwd m14, m10, m2
+ paddd m12, m14
+ paddd m9, m12
+ paddd m9, m6
+ psrad m9, INTERP_SHIFT_PS
+
+ packssdw m8, m9
+ pshufb m8, m7
+ movu [r2 + 2 * r3], ym8
+ vextracti32x8 [r2 + r7], m8, 1
+%endmacro
+
+%macro PROCESS_IPFILTER_LUMA_PS_16x3_AVX512 0
+ movu ym8, [r0]
+ vinserti32x8 m8, [r0 + r1], 1
+ movu ym9, [r0 + 8]
+ vinserti32x8 m9, [r0 + r1 + 8], 1
+ movu ym10, [r0 + 16]
+ vinserti32x8 m10, [r0 + r1 + 16], 1
+
+ pshufb m11, m8, m5
+ pshufb m8, m4
+ pshufb m12, m9, m5
+ pshufb m9, m4
+ pshufb m13, m10, m5
+ pshufb m10, m4
+
+ pmaddwd m8, m0
+ pmaddwd m11, m1
+ paddd m8, m11
+ pmaddwd m11, m12, m3
+ pmaddwd m14, m9, m2
+ paddd m11, m14
+ paddd m8, m11
+ paddd m8, m6
+ psrad m8, INTERP_SHIFT_PS
+
+ pmaddwd m9, m0
+ pmaddwd m12, m1
+ paddd m9, m12
+ pmaddwd m13, m3
+ pmaddwd m10, m2
+ paddd m10, m13
+ paddd m9, m10
+ paddd m9, m6
+ psrad m9, INTERP_SHIFT_PS
+
+ packssdw m8, m9
+ pshufb m8, m7
+ movu [r2], ym8
+ vextracti32x8 [r2 + r3],m8, 1
+
+ movu ym8, [r0 + 2 * r1]
+ movu ym9, [r0 + 2 * r1 + 8]
+ movu ym10, [r0 + 2 * r1 + 16]
+
+ pshufb ym11, ym8, ym5
+ pshufb ym8, ym4
+ pshufb ym12, ym9, ym5
+ pshufb ym9, ym4
+ pshufb ym13, ym10, ym5
+ pshufb ym10, ym4
+
+ pmaddwd ym8, ym0
+ pmaddwd ym11, ym1
+ paddd ym8, ym11
+ pmaddwd ym11, ym12, ym3
+ pmaddwd ym14, ym9, ym2
+ paddd ym11, ym14
+ paddd ym8, ym11
+ paddd ym8, ym6
+ psrad ym8, INTERP_SHIFT_PS
+
+ pmaddwd ym9, ym0
+ pmaddwd ym12, ym1
+ paddd ym9, ym12
+ pmaddwd ym12, ym13, ym3
+ pmaddwd ym14, ym10, ym2
+ paddd ym12, ym14
+ paddd ym9, ym12
+ paddd ym9, ym6
+ psrad ym9, INTERP_SHIFT_PS
+
+ packssdw ym8, ym9
+ pshufb ym8, ym7
+ movu [r2 + 2 * r3], ym8
+%endmacro
+
+
+%macro IPFILTER_LUMA_PS_AVX512_16xN 1
+INIT_ZMM avx512
+cglobal interp_8tap_horiz_ps_16x%1, 4,9,15
+ add r1d, r1d
+ add r3d, r3d
+ mov r4d, r4m
+ mov r5d, r5m
+ shl r4d, 6
+
+ lea r6, [3 * r1]
+ lea r7, [3 * r3]
+%ifdef PIC
+ lea r8, [tab_LumaCoeffH_avx512]
+ vpbroadcastd m0, [r8 + r4]
+ vpbroadcastd m1, [r8 + r4 + 4]
+ vpbroadcastd m2, [r8 + r4 + 8]
+ vpbroadcastd m3, [r8 + r4 + 12]
+%else
+ vpbroadcastd m0, [tab_LumaCoeffH_avx512 + r4]
+ vpbroadcastd m1, [tab_LumaCoeffH_avx512 + r4 + 4]
+ vpbroadcastd m2, [tab_LumaCoeffH_avx512 + r4 + 8]
+ vpbroadcastd m3, [tab_LumaCoeffH_avx512 + r4 + 12]
+%endif
+ vbroadcasti32x8 m4, [interp8_hpp_shuf1_load_avx512]
+ vbroadcasti32x8 m5, [interp8_hpp_shuf2_load_avx512]
+ vbroadcasti32x8 m6, [INTERP_OFFSET_PS]
+ vbroadcasti32x8 m7, [interp8_hpp_shuf1_store_avx512]
+
+ sub r0, 6
+ mov r4d, %1
+ test r5d, r5d
+ jz .loop
+ lea r6, [r1 * 3]
+ sub r0, r6
+ add r4d, 7
+ PROCESS_IPFILTER_LUMA_PS_16x3_AVX512
+ lea r0, [r0 + r6]
+ lea r2, [r2 + r7]
+ sub r4d, 3
+
+.loop:
+ PROCESS_IPFILTER_LUMA_PS_16x4_AVX512
+ lea r0, [r0 + 4 * r1]
+ lea r2, [r2 + 4 * r3]
+ sub r4d, 4
+ jnz .loop
+ RET
+%endmacro
+
+%if ARCH_X86_64
+IPFILTER_LUMA_PS_AVX512_16xN 4
+IPFILTER_LUMA_PS_AVX512_16xN 8
+IPFILTER_LUMA_PS_AVX512_16xN 12
+IPFILTER_LUMA_PS_AVX512_16xN 16
+IPFILTER_LUMA_PS_AVX512_16xN 32
+IPFILTER_LUMA_PS_AVX512_16xN 64
+%endif
+
;-------------------------------------------------------------------------------------------------------------
;avx512 luma_hps code end
;-------------------------------------------------------------------------------------------------------------
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