[x265] [PATCH 237 of 307] x86: AVX512 interp_8tap_vert_pp_64xN and interp_8tap_vert_ps_64xN for high bit depth

mythreyi at multicorewareinc.com mythreyi at multicorewareinc.com
Sat Apr 7 04:33:55 CEST 2018


# HG changeset patch
# User Vignesh Vijayakumar<vignesh at multicorewareinc.com>
# Date 1512460722 -19800
#      Tue Dec 05 13:28:42 2017 +0530
# Node ID ca6bb5919227672e0cf98b785acf099531c32945
# Parent  c3a341391f0c777665e191a4cd172f08a5a313f9
x86: AVX512 interp_8tap_vert_pp_64xN  and interp_8tap_vert_ps_64xN for high bit depth

luma_vpp
Size  |  AVX2 performance  | AVX512 performance
----------------------------------------------
64x16 |       11.51x       |      19.67x
64x32 |       11.51x       |      19.42x
64x48 |       11.54x       |      19.42x
64x64 |       11.55x       |      19.72x

luma_vps
Size  |  AVX2 performance  | AVX512 performance
----------------------------------------------
64x16 |        9.92x       |      18.23x
64x32 |        9.71x       |      18.13x
64x48 |        9.81x       |      18.04x
64x64 |        9.86x       |      18.14x

diff -r c3a341391f0c -r ca6bb5919227 source/common/x86/asm-primitives.cpp
--- a/source/common/x86/asm-primitives.cpp	Fri Nov 24 16:44:56 2017 +0530
+++ b/source/common/x86/asm-primitives.cpp	Tue Dec 05 13:28:42 2017 +0530
@@ -2887,12 +2887,20 @@
         p.pu[LUMA_32x32].luma_vpp = PFX(interp_8tap_vert_pp_32x32_avx512);
         p.pu[LUMA_32x24].luma_vpp = PFX(interp_8tap_vert_pp_32x24_avx512);
         p.pu[LUMA_32x64].luma_vpp = PFX(interp_8tap_vert_pp_32x64_avx512);
+        p.pu[LUMA_64x16].luma_vpp = PFX(interp_8tap_vert_pp_64x16_avx512);
+        p.pu[LUMA_64x32].luma_vpp = PFX(interp_8tap_vert_pp_64x32_avx512);
+        p.pu[LUMA_64x48].luma_vpp = PFX(interp_8tap_vert_pp_64x48_avx512);
+        p.pu[LUMA_64x64].luma_vpp = PFX(interp_8tap_vert_pp_64x64_avx512);
 
         p.pu[LUMA_32x8].luma_vps = PFX(interp_8tap_vert_ps_32x8_avx512);
         p.pu[LUMA_32x16].luma_vps = PFX(interp_8tap_vert_ps_32x16_avx512);
         p.pu[LUMA_32x32].luma_vps = PFX(interp_8tap_vert_ps_32x32_avx512);
         p.pu[LUMA_32x24].luma_vps = PFX(interp_8tap_vert_ps_32x24_avx512);
         p.pu[LUMA_32x64].luma_vps = PFX(interp_8tap_vert_ps_32x64_avx512);
+        p.pu[LUMA_64x16].luma_vps = PFX(interp_8tap_vert_ps_64x16_avx512);
+        p.pu[LUMA_64x32].luma_vps = PFX(interp_8tap_vert_ps_64x32_avx512);
+        p.pu[LUMA_64x48].luma_vps = PFX(interp_8tap_vert_ps_64x48_avx512);
+        p.pu[LUMA_64x64].luma_vps = PFX(interp_8tap_vert_ps_64x64_avx512);
 
         p.cu[BLOCK_8x8].dct = PFX(dct8_avx512);
         /* TODO: Currently these kernels performance are similar to AVX2 version, we need a to improve them further to ebable
diff -r c3a341391f0c -r ca6bb5919227 source/common/x86/ipfilter16.asm
--- a/source/common/x86/ipfilter16.asm	Fri Nov 24 16:44:56 2017 +0530
+++ b/source/common/x86/ipfilter16.asm	Tue Dec 05 13:28:42 2017 +0530
@@ -13078,6 +13078,152 @@
     FILTER_VER_P_LUMA_32xN_AVX512 pp, 24
     FILTER_VER_P_LUMA_32xN_AVX512 pp, 64
 %endif
+
+%macro PROCESS_LUMA_VERT_P_64x2_AVX512 1
+    PROCESS_LUMA_VERT_P_32x2_AVX512 %1
+    movu                 m1,                  [r0 + mmsize]
+    movu                 m3,                  [r0 + r1 + mmsize]
+    punpcklwd            m0,                  m1,                     m3
+    pmaddwd              m0,                  m15
+    punpckhwd            m1,                  m3
+    pmaddwd              m1,                  m15
+
+    movu                 m4,                  [r0 + 2 * r1 + mmsize]
+    punpcklwd            m2,                  m3,                     m4
+    pmaddwd              m2,                  m15
+    punpckhwd            m3,                  m4
+    pmaddwd              m3,                  m15
+
+    movu                 m5,                  [r0 + r7 + mmsize]
+    punpcklwd            m6,                  m4,                     m5
+    pmaddwd              m6,                  m16
+    punpckhwd            m4,                  m5
+    pmaddwd              m4,                  m16
+
+    paddd                m0,                  m6
+    paddd                m1,                  m4
+
+    movu                 m4,                  [r0 + 4 * r1 + mmsize]
+    punpcklwd            m6,                  m5,                     m4
+    pmaddwd              m6,                  m16
+    punpckhwd            m5,                  m4
+    pmaddwd              m5,                  m16
+
+    paddd                m2,                  m6
+    paddd                m3,                  m5
+
+    movu                 m11,                 [r6 + r1 + mmsize]
+    punpcklwd            m8,                  m4,                     m11
+    pmaddwd              m8,                  m17
+    punpckhwd            m4,                  m11
+    pmaddwd              m4,                  m17
+
+    movu                 m12,                 [r6 + 2 * r1 + mmsize]
+    punpcklwd            m10,                 m11,                    m12
+    pmaddwd              m10,                 m17
+    punpckhwd            m11,                 m12
+    pmaddwd              m11,                 m17
+
+    movu                 m13,                 [r6 + r7 + mmsize]
+    punpcklwd            m14,                 m12,                    m13
+    pmaddwd              m14,                 m18
+    punpckhwd            m12,                 m13
+    pmaddwd              m12,                 m18
+
+    paddd                m8,                  m14
+    paddd                m4,                  m12
+    paddd                m0,                  m8
+    paddd                m1,                  m4
+
+    movu                 m12,                 [r6 + 4 * r1 + mmsize]
+    punpcklwd            m14,                 m13,                    m12
+    pmaddwd              m14,                 m18
+    punpckhwd            m13,                 m12
+    pmaddwd              m13,                 m18
+
+    paddd                m10,                 m14
+    paddd                m11,                 m13
+    paddd                m2,                  m10
+    paddd                m3,                  m11
+
+    paddd                m0,                  m19
+    paddd                m1,                  m19
+    paddd                m2,                  m19
+    paddd                m3,                  m19
+
+%ifidn %1, pp
+    psrad                m0,                  INTERP_SHIFT_PP
+    psrad                m1,                  INTERP_SHIFT_PP
+    psrad                m2,                  INTERP_SHIFT_PP
+    psrad                m3,                  INTERP_SHIFT_PP
+
+    packssdw             m0,                  m1
+    packssdw             m2,                  m3
+    CLIPW2               m0,                  m2,                   m20,                 m21
+%else
+    psrad                m0,                  INTERP_SHIFT_PS
+    psrad                m1,                  INTERP_SHIFT_PS
+    psrad                m2,                  INTERP_SHIFT_PS
+    psrad                m3,                  INTERP_SHIFT_PS
+
+    packssdw             m0,                  m1
+    packssdw             m2,                  m3
+%endif
+
+    movu                 [r2 + mmsize],       m0
+    movu                 [r2 + r3 + mmsize],  m2
+%endmacro
+;-----------------------------------------------------------------------------------------------------------------
+; void interp_8tap_vert(int16_t *src, intptr_t srcStride, int16_t *dst, intptr_t dstStride, int coeffIdx)
+;-----------------------------------------------------------------------------------------------------------------
+%macro FILTER_VER_P_LUMA_64xN_AVX512 2
+INIT_ZMM avx512
+cglobal interp_8tap_vert_%1_64x%2, 5, 8, 22
+    add                   r1d,                r1d
+    add                   r3d,                r3d
+    shl                   r4d,                8
+%ifdef PIC
+    lea                   r5,                 [tab_LumaCoeffVer_avx512]
+    mova                  m15,                [r5 + r4]
+    mova                  m16,                [r5 + r4 + 1 * mmsize]
+    mova                  m17,                [r5 + r4 + 2 * mmsize]
+    mova                  m18,                [r5 + r4 + 3 * mmsize]
+%else
+    lea                   r5,                 [tab_LumaCoeffVer_avx512 + r4]
+    mova                  m15,                [r5]
+    mova                  m16,                [r5 + 1 * mmsize]
+    mova                  m17,                [r5 + 2 * mmsize]
+    mova                  m18,                [r5 + 3 * mmsize]
+%endif
+%ifidn %1, pp
+    vbroadcasti32x4       m19,                [INTERP_OFFSET_PP]
+    pxor                  m20,                m20
+    vbroadcasti32x8       m21,                [pw_pixel_max]
+%else
+    vbroadcasti32x4       m19,                [INTERP_OFFSET_PS]
+%endif
+    lea                   r7,                 [3 * r1]
+    sub                   r0,                 r7
+
+%rep %2/2 - 1
+    PROCESS_LUMA_VERT_P_64x2_AVX512 %1
+    lea                   r0,                 [r0 + 2 * r1]
+    lea                   r2,                 [r2 + 2 * r3]
+%endrep
+    PROCESS_LUMA_VERT_P_64x2_AVX512 %1
+    RET
+%endmacro
+
+%if ARCH_X86_64
+    FILTER_VER_P_LUMA_64xN_AVX512 ps, 16
+    FILTER_VER_P_LUMA_64xN_AVX512 ps, 32
+    FILTER_VER_P_LUMA_64xN_AVX512 ps, 48
+    FILTER_VER_P_LUMA_64xN_AVX512 ps, 64
+    FILTER_VER_P_LUMA_64xN_AVX512 pp, 16
+    FILTER_VER_P_LUMA_64xN_AVX512 pp, 32
+    FILTER_VER_P_LUMA_64xN_AVX512 pp, 48
+    FILTER_VER_P_LUMA_64xN_AVX512 pp, 64
+%endif
 ;-------------------------------------------------------------------------------------------------------------
 ;avx512 luma_vpp and luma_vps code end
 ;-------------------------------------------------------------------------------------------------------------


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