[x265] [PATCH 239 of 307] x86: AVX512 interp_8tap_vert_pp_48x64 and interp_8tap_vert_ps_48x64 for high bit depth
mythreyi at multicorewareinc.com
mythreyi at multicorewareinc.com
Sat Apr 7 04:33:57 CEST 2018
# HG changeset patch
# User Vignesh Vijayakumar<vignesh at multicorewareinc.com>
# Date 1512475230 -19800
# Tue Dec 05 17:30:30 2017 +0530
# Node ID 8b1c9d9c5bd8135dc11b6d031b990bfe47e3bcd8
# Parent f92128e41ac3c1da210c1c665d97061539821aaf
x86: AVX512 interp_8tap_vert_pp_48x64 and interp_8tap_vert_ps_48x64 for high bit depth
luma_vpp_48x64
AVX2 performance : 11.60x
AVX512 performance : 18.57x
luma_vps_48x64
AVX2 performance : 9.97x
AVX512 performance : 17.28x
diff -r f92128e41ac3 -r 8b1c9d9c5bd8 source/common/x86/asm-primitives.cpp
--- a/source/common/x86/asm-primitives.cpp Tue Dec 05 14:41:07 2017 +0530
+++ b/source/common/x86/asm-primitives.cpp Tue Dec 05 17:30:30 2017 +0530
@@ -2893,6 +2893,7 @@
p.pu[LUMA_32x32].luma_vpp = PFX(interp_8tap_vert_pp_32x32_avx512);
p.pu[LUMA_32x24].luma_vpp = PFX(interp_8tap_vert_pp_32x24_avx512);
p.pu[LUMA_32x64].luma_vpp = PFX(interp_8tap_vert_pp_32x64_avx512);
+ p.pu[LUMA_48x64].luma_vpp = PFX(interp_8tap_vert_pp_48x64_avx512);
p.pu[LUMA_64x16].luma_vpp = PFX(interp_8tap_vert_pp_64x16_avx512);
p.pu[LUMA_64x32].luma_vpp = PFX(interp_8tap_vert_pp_64x32_avx512);
p.pu[LUMA_64x48].luma_vpp = PFX(interp_8tap_vert_pp_64x48_avx512);
@@ -2909,6 +2910,7 @@
p.pu[LUMA_32x32].luma_vps = PFX(interp_8tap_vert_ps_32x32_avx512);
p.pu[LUMA_32x24].luma_vps = PFX(interp_8tap_vert_ps_32x24_avx512);
p.pu[LUMA_32x64].luma_vps = PFX(interp_8tap_vert_ps_32x64_avx512);
+ p.pu[LUMA_48x64].luma_vps = PFX(interp_8tap_vert_ps_48x64_avx512);
p.pu[LUMA_64x16].luma_vps = PFX(interp_8tap_vert_ps_64x16_avx512);
p.pu[LUMA_64x32].luma_vps = PFX(interp_8tap_vert_ps_64x32_avx512);
p.pu[LUMA_64x48].luma_vps = PFX(interp_8tap_vert_ps_64x48_avx512);
diff -r f92128e41ac3 -r 8b1c9d9c5bd8 source/common/x86/ipfilter16.asm
--- a/source/common/x86/ipfilter16.asm Tue Dec 05 14:41:07 2017 +0530
+++ b/source/common/x86/ipfilter16.asm Tue Dec 05 17:30:30 2017 +0530
@@ -13242,6 +13242,251 @@
FILTER_VER_P_LUMA_32xN_AVX512 pp, 64
%endif
+%macro PROCESS_LUMA_VERT_P_48x4_AVX512 1
+ PROCESS_LUMA_VERT_P_32x2_AVX512 %1
+ movu m1, [r0 + 2 * r1]
+ movu m3, [r0 + r7]
+ punpcklwd m0, m1, m3
+ pmaddwd m0, m15
+ punpckhwd m1, m3
+ pmaddwd m1, m15
+
+ movu m4, [r0 + 4 * r1]
+ punpcklwd m2, m3, m4
+ pmaddwd m2, m15
+ punpckhwd m3, m4
+ pmaddwd m3, m15
+
+ movu m5, [r6 + r1]
+ punpcklwd m6, m4, m5
+ pmaddwd m6, m16
+ punpckhwd m4, m5
+ pmaddwd m4, m16
+
+ paddd m0, m6
+ paddd m1, m4
+
+ movu m4, [r6 + 2 * r1]
+ punpcklwd m6, m5, m4
+ pmaddwd m6, m16
+ punpckhwd m5, m4
+ pmaddwd m5, m16
+
+ paddd m2, m6
+ paddd m3, m5
+
+ lea r4, [r6 + 4 * r1]
+
+ movu m11, [r6 + r7]
+ punpcklwd m8, m4, m11
+ pmaddwd m8, m17
+ punpckhwd m4, m11
+ pmaddwd m4, m17
+
+ movu m12, [r6 + 4 * r1]
+ punpcklwd m10, m11, m12
+ pmaddwd m10, m17
+ punpckhwd m11, m12
+ pmaddwd m11, m17
+
+ movu m13, [r4 + r1]
+ punpcklwd m14, m12, m13
+ pmaddwd m14, m18
+ punpckhwd m12, m13
+ pmaddwd m12, m18
+
+ paddd m8, m14
+ paddd m4, m12
+ paddd m0, m8
+ paddd m1, m4
+
+ movu m12, [r4 + 2 * r1]
+ punpcklwd m14, m13, m12
+ pmaddwd m14, m18
+ punpckhwd m13, m12
+ pmaddwd m13, m18
+
+ paddd m10, m14
+ paddd m11, m13
+ paddd m2, m10
+ paddd m3, m11
+
+ paddd m0, m19
+ paddd m1, m19
+ paddd m2, m19
+ paddd m3, m19
+
+%ifidn %1, pp
+ psrad m0, INTERP_SHIFT_PP
+ psrad m1, INTERP_SHIFT_PP
+ psrad m2, INTERP_SHIFT_PP
+ psrad m3, INTERP_SHIFT_PP
+
+ packssdw m0, m1
+ packssdw m2, m3
+ CLIPW2 m0, m2, m20, m21
+%else
+ psrad m0, INTERP_SHIFT_PS
+ psrad m1, INTERP_SHIFT_PS
+ psrad m2, INTERP_SHIFT_PS
+ psrad m3, INTERP_SHIFT_PS
+
+ packssdw m0, m1
+ packssdw m2, m3
+%endif
+ movu [r2 + 2 * r3], m0
+ movu [r2 + r8], m2
+
+ movu ym1, [r0 + mmsize]
+ movu ym3, [r0 + r1 + mmsize]
+ vinserti32x8 m1, [r0 + 2 * r1 + mmsize], 1
+ vinserti32x8 m3, [r0 + r7 + mmsize], 1
+ punpcklwd m0, m1, m3
+ pmaddwd m0, m15
+ punpckhwd m1, m3
+ pmaddwd m1, m15
+
+ movu ym4, [r0 + 2 * r1 + mmsize]
+ vinserti32x8 m4, [r0 + 4 * r1 + mmsize], 1
+ punpcklwd m2, m3, m4
+ pmaddwd m2, m15
+ punpckhwd m3, m4
+ pmaddwd m3, m15
+
+ movu ym5, [r0 + r7 + mmsize]
+ vinserti32x8 m5, [r6 + r1 + mmsize], 1
+ punpcklwd m6, m4, m5
+ pmaddwd m6, m16
+ punpckhwd m4, m5
+ pmaddwd m4, m16
+
+ paddd m0, m6
+ paddd m1, m4
+
+ movu ym4, [r6 + mmsize]
+ vinserti32x8 m4, [r6 + 2 * r1 + mmsize], 1
+ punpcklwd m6, m5, m4
+ pmaddwd m6, m16
+ punpckhwd m5, m4
+ pmaddwd m5, m16
+
+ paddd m2, m6
+ paddd m3, m5
+
+ movu ym11, [r6 + r1 + mmsize]
+ vinserti32x8 m11, [r6 + r7 + mmsize], 1
+ punpcklwd m8, m4, m11
+ pmaddwd m8, m17
+ punpckhwd m4, m11
+ pmaddwd m4, m17
+
+ movu ym12, [r6 + 2 * r1 + mmsize]
+ vinserti32x8 m12, [r4 + mmsize], 1
+ punpcklwd m10, m11, m12
+ pmaddwd m10, m17
+ punpckhwd m11, m12
+ pmaddwd m11, m17
+
+ movu ym13, [r6 + r7 + mmsize]
+ vinserti32x8 m13, [r4 + r1 + mmsize], 1
+ punpcklwd m14, m12, m13
+ pmaddwd m14, m18
+ punpckhwd m12, m13
+ pmaddwd m12, m18
+
+ paddd m8, m14
+ paddd m4, m12
+ paddd m0, m8
+ paddd m1, m4
+
+ movu ym12, [r4 + mmsize]
+ vinserti32x8 m12, [r4 + 2 * r1 + mmsize], 1
+ punpcklwd m14, m13, m12
+ pmaddwd m14, m18
+ punpckhwd m13, m12
+ pmaddwd m13, m18
+
+ paddd m10, m14
+ paddd m11, m13
+ paddd m2, m10
+ paddd m3, m11
+
+ paddd m0, m19
+ paddd m1, m19
+ paddd m2, m19
+ paddd m3, m19
+
+%ifidn %1, pp
+ psrad m0, INTERP_SHIFT_PP
+ psrad m1, INTERP_SHIFT_PP
+ psrad m2, INTERP_SHIFT_PP
+ psrad m3, INTERP_SHIFT_PP
+
+ packssdw m0, m1
+ packssdw m2, m3
+ CLIPW2 m0, m2, m20, m21
+%else
+ psrad m0, INTERP_SHIFT_PS
+ psrad m1, INTERP_SHIFT_PS
+ psrad m2, INTERP_SHIFT_PS
+ psrad m3, INTERP_SHIFT_PS
+
+ packssdw m0, m1
+ packssdw m2, m3
+%endif
+
+ movu [r2 + mmsize], ym0
+ movu [r2 + r3 + mmsize], ym2
+ vextracti32x8 [r2 + 2 * r3 + mmsize], m0, 1
+ vextracti32x8 [r2 + r8 + mmsize], m2, 1
+%endmacro
+;-----------------------------------------------------------------------------------------------------------------
+; void interp_4tap_vert(int16_t *src, intptr_t srcStride, int16_t *dst, intptr_t dstStride, int coeffIdx)
+;-----------------------------------------------------------------------------------------------------------------
+%macro FILTER_VER_P_LUMA_48x64_AVX512 1
+INIT_ZMM avx512
+cglobal interp_8tap_vert_%1_48x64, 5, 9, 22
+ add r1d, r1d
+ add r3d, r3d
+ shl r4d, 8
+%ifdef PIC
+ lea r5, [tab_LumaCoeffVer_avx512]
+ mova m15, [r5 + r4]
+ mova m16, [r5 + r4 + 1 * mmsize]
+ mova m17, [r5 + r4 + 2 * mmsize]
+ mova m18, [r5 + r4 + 3 * mmsize]
+%else
+ lea r5, [tab_LumaCoeffVer_avx512 + r4]
+ mova m15, [r5]
+ mova m16, [r5 + 1 * mmsize]
+ mova m17, [r5 + 2 * mmsize]
+ mova m18, [r5 + 3 * mmsize]
+%endif
+%ifidn %1, pp
+ vbroadcasti32x4 m19, [INTERP_OFFSET_PP]
+ pxor m20, m20
+ vbroadcasti32x8 m21, [pw_pixel_max]
+%else
+ vbroadcasti32x4 m19, [INTERP_OFFSET_PS]
+%endif
+ lea r7, [3 * r1]
+ lea r8, [3 * r3]
+ sub r0, r7
+
+%rep 15
+ PROCESS_LUMA_VERT_P_48x4_AVX512 %1
+ lea r0, [r0 + 4 * r1]
+ lea r2, [r2 + 4 * r3]
+%endrep
+ PROCESS_LUMA_VERT_P_48x4_AVX512 %1
+ RET
+%endmacro
+
+%if ARCH_X86_64
+ FILTER_VER_P_LUMA_48x64_AVX512 ps
+ FILTER_VER_P_LUMA_48x64_AVX512 pp
+%endif
+
%macro PROCESS_LUMA_VERT_P_64x2_AVX512 1
PROCESS_LUMA_VERT_P_32x2_AVX512 %1
movu m1, [r0 + mmsize]
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