[x265] [PATCH Review only] asm: pixel_add_pp routine for block sizes 32x8, 32x16, 32x24, 32x32 and 32x64

[murugan at multicorewareinc.com]

# HG changeset patch
# User Murugan Vairavel <murugan at multicorewareinc.com>
# Date 1383724042 -19800
#      Wed Nov 06 13:17:22 2013 +0530
# Node ID d14d18379efbeb4b77e84e66e809c8d02715530e
# Parent  e025d0e905a28d8517bd13303d157a6139ded651
asm: pixel_add_pp routine for block sizes 32x8, 32x16, 32x24, 32x32 and 32x64

diff -r e025d0e905a2 -r d14d18379efb source/common/x86/pixel-add8.asm
--- a/source/common/x86/pixel-add8.asm	Wed Nov 06 12:59:57 2013 +0530
+++ b/source/common/x86/pixel-add8.asm	Wed Nov 06 13:17:22 2013 +0530
@@ -484,3 +484,54 @@
 %endmacro
 
 PIXELADD_PP_W24_H2 24, 32
+
+;-----------------------------------------------------------------------------
+; void pixel_add_pp_c_%1x%2(pixel *dest, intptr_t destride, pixel *src0, pixel *src1, intptr_t srcstride0, intptr_t srcstride1);
+;-----------------------------------------------------------------------------
+%macro PIXELADD_PP_W32_H2 2
+INIT_XMM sse2
+cglobal pixel_add_pp_%1x%2, 4, 7, 8, dest, deststride, src0, src1
+
+mov    r4d,    r4m
+mov    r5d,    r5m
+mov    r6d,    %2
+
+.loop
+
+    movu       m0,    [r2]
+    movu       m1,    [r2 + 16]
+    movu       m2,    [r3]
+    movu       m3,    [r3 + 16]
+
+    movu       m4,    [r2 + r4]
+    movu       m5,    [r2 + r4 + 16]
+    movu       m6,    [r3 + r5]
+    movu       m7,    [r3 + r5 + 16]
+
+    paddusb    m0,    m2
+    paddusb    m1,    m3
+    paddusb    m4,    m6
+    paddusb    m5,    m7
+
+    movu    [r0],              m0
+    movu    [r0 + 16],         m1
+    movu    [r0 + r1],         m4
+    movu    [r0 + r1 + 16],    m5
+
+    lea     r2,                [r2 + 2 * r4]
+    lea     r3,                [r3 + 2 * r5]
+    lea     r0,                [r0 + 2 * r1]
+
+    sub     r6d,               2
+
+jnz    .loop
+
+RET
+%endmacro
+
+PIXELADD_PP_W32_H2 32, 8
+PIXELADD_PP_W32_H2 32, 16
+PIXELADD_PP_W32_H2 32, 24
+PIXELADD_PP_W32_H2 32, 32
+PIXELADD_PP_W32_H2 32, 64
+