[x265] [PATCH Review only] asm: pixelsub_ps routine for 24x32 block

[murugan at multicorewareinc.com]

# HG changeset patch
# User Murugan Vairavel <murugan at multicorewareinc.com>
# Date 1383920521 -19800
#      Fri Nov 08 19:52:01 2013 +0530
# Node ID cafaa193236cfc39540dbf702260fe66a6cb262c
# Parent  2276504f3cf3d0ddad4273771a87dbcecc47b21f
asm: pixelsub_ps routine for 24x32 block

diff -r 2276504f3cf3 -r cafaa193236c source/common/x86/pixel-a.asm
--- a/source/common/x86/pixel-a.asm	Fri Nov 08 17:35:04 2013 +0530
+++ b/source/common/x86/pixel-a.asm	Fri Nov 08 19:52:01 2013 +0530
@@ -5804,3 +5804,72 @@
 PIXELSUB_PS_W16_H4 16, 16
 PIXELSUB_PS_W16_H4 16, 32
 PIXELSUB_PS_W16_H4 16, 64
+
+;-----------------------------------------------------------------------------
+; void pixel_sub_ps_c_%1x%2(pixel *dest, intptr_t destride, pixel *src0, pixel *src1, intptr_t srcstride0, intptr_t srcstride1);
+;-----------------------------------------------------------------------------
+%macro PIXELSUB_PS_W24_H2 2
+INIT_XMM sse4
+cglobal pixel_sub_ps_%1x%2, 6, 7, 6, dest, deststride, src0, src1, srcstride0, srcstride1
+
+add    r1,     r1
+mov    r6d,    %2/2
+
+.loop
+
+    movh        m0,    [r2]
+    movh        m1,    [r2 + 8]
+    movh        m2,    [r2 + 16]
+    movh        m3,    [r3]
+    movh        m4,    [r3 + 8]
+    movh        m5,    [r3 + 16]
+
+    pmovzxbw    m0,    m0
+    pmovzxbw    m1,    m1
+    pmovzxbw    m2,    m2
+    pmovzxbw    m3,    m3
+    pmovzxbw    m4,    m4
+    pmovzxbw    m5,    m5
+
+    psubw       m0,    m3
+    psubw       m1,    m4
+    psubw       m2,    m5
+
+    movu    [r0],         m0
+    movu    [r0 + 16],    m1
+    movu    [r0 + 32],    m2
+
+    movh        m0,    [r2 + r4]
+    movh        m1,    [r2 + r4 + 8]
+    movh        m2,    [r2 + r4 + 16]
+    movh        m3,    [r3 + r5]
+    movh        m4,    [r3 + r5 + 8]
+    movh        m5,    [r3 + r5 + 16]
+
+    pmovzxbw    m0,    m0
+    pmovzxbw    m1,    m1
+    pmovzxbw    m2,    m2
+    pmovzxbw    m3,    m3
+    pmovzxbw    m4,    m4
+    pmovzxbw    m5,    m5
+
+    psubw       m0,    m3
+    psubw       m1,    m4
+    psubw       m2,    m5
+
+    movu    [r0 + r1],         m0
+    movu    [r0 + r1 + 16],    m1
+    movu    [r0 + r1 + 32],    m2
+
+    lea    r2,    [r2 + 2 * r4]
+    lea    r3,    [r3 + 2 * r5]
+    lea    r0,    [r0 + 2 * r1]
+
+    dec    r6d
+
+jnz    .loop
+
+RET
+%endmacro
+
+PIXELSUB_PS_W24_H2 24, 32