[x265] [PATCH] blockcopy_sp_48x64, optimized asm code

praveen at multicorewareinc.com praveen at multicorewareinc.com
Fri Nov 8 16:47:22 CET 2013


# HG changeset patch
# User Praveen Tiwari
# Date 1383925633 -19800
# Node ID fae2b7777b9ee77cc8ad1b1e118b679964b567b9
# Parent  241c644e7b5dcd87e6a17d8e8a71aa771c99fb4a
blockcopy_sp_48x64, optimized asm code

diff -r 241c644e7b5d -r fae2b7777b9e source/common/x86/blockcopy8.asm
--- a/source/common/x86/blockcopy8.asm	Fri Nov 08 20:58:14 2013 +0530
+++ b/source/common/x86/blockcopy8.asm	Fri Nov 08 21:17:13 2013 +0530
@@ -1470,61 +1470,32 @@
 ;-----------------------------------------------------------------------------
 %macro BLOCKCOPY_SP_W48_H2 2
 INIT_XMM sse2
-cglobal blockcopy_sp_%1x%2, 4, 5, 7, dest, destStride, src, srcStride
+cglobal blockcopy_sp_%1x%2, 4, 5, 6, dest, destStride, src, srcStride
 
-mov         r4d,    %2
+mov             r4d,     %2
 
-add        r3,      r3
-
-mova       m0,      [tab_Vm]
+add             r3,      r3
 
 .loop
-     movu       m1,      [r2]
-     movu       m2,      [r2 + 16]
-     movu       m3,      [r2 + 32]
-     movu       m4,      [r2 + 48]
-     movu       m5,      [r2 + 64]
-     movu       m6,      [r2 + 80]
+     movu       m0,        [r2]
+     movu       m1,        [r2 + 16]
+     movu       m2,        [r2 + 32]
+     movu       m3,        [r2 + 48]
+     movu       m4,        [r2 + 64]
+     movu       m5,        [r2 + 80]
 
-     pshufb     m1,      m0
-     pshufb     m2,      m0
-     pshufb     m3,      m0
-     pshufb     m4,      m0
-     pshufb     m5,      m0
-     pshufb     m6,      m0
+     packuswb   m0,        m1
+     packuswb   m2,        m3
+     packuswb   m4,        m5
 
-     movh       [r0],              m1
-     movh       [r0 + 8],          m2
-     movh       [r0 + 16],         m3
-     movh       [r0 + 24],         m4
-     movh       [r0 + 32],         m5
-     movh       [r0 + 40],         m6
+     movu       [r0],      m0
+     movu       [r0 + 16], m2
+     movu       [r0 + 32], m4
 
-     movu       m1,      [r2 + r3]
-     movu       m2,      [r2 + r3 + 16]
-     movu       m3,      [r2 + r3 + 32]
-     movu       m4,      [r2 + r3 + 48]
-     movu       m5,      [r2 + r3 + 64]
-     movu       m6,      [r2 + r3 + 80]
+     lea        r0,        [r0 + r1]
+     lea        r2,        [r2 + r3]
 
-     pshufb     m1,      m0
-     pshufb     m2,      m0
-     pshufb     m3,      m0
-     pshufb     m4,      m0
-     pshufb     m5,      m0
-     pshufb     m6,      m0
-
-     movh       [r0 + r1],              m1
-     movh       [r0 + r1 + 8],          m2
-     movh       [r0 + r1 + 16],         m3
-     movh       [r0 + r1 + 24],         m4
-     movh       [r0 + r1 + 32],         m5
-     movh       [r0 + r1 + 40],         m6
-
-     lea        r0,              [r0 + 2 * r1]
-     lea        r2,              [r2 + 2 * r3]
-
-     sub        r4d,             2
+     dec        r4d
      jnz        .loop
 
 RET
@@ -1541,7 +1512,7 @@
 
 mov             r4d,       %2
 
-add             r3,        r3
+add             r3,         r3
 
 .loop
       movu      m0,        [r2]


More information about the x265-devel mailing list