[x265] [PATCH Review only] asm: code for pixel_sse_16xN routines
murugan at multicorewareinc.com
murugan at multicorewareinc.com
Tue Nov 26 13:16:56 CET 2013
# HG changeset patch
# User Murugan Vairavel <murugan at multicorewareinc.com>
# Date 1385468184 -19800
# Tue Nov 26 17:46:24 2013 +0530
# Node ID b4be37816bb4ab8afe9e60e08ab84a4ee28a6d0f
# Parent e17784926dd2a5a3145557655c979fd564308fb2
asm: code for pixel_sse_16xN routines
diff -r e17784926dd2 -r b4be37816bb4 source/common/x86/asm-primitives.cpp
--- a/source/common/x86/asm-primitives.cpp Tue Nov 26 13:31:22 2013 +0530
+++ b/source/common/x86/asm-primitives.cpp Tue Nov 26 17:46:24 2013 +0530
@@ -612,6 +612,13 @@
p.sse_pp[LUMA_64x48] = x265_pixel_ssd_64x48_sse4;
p.sse_pp[LUMA_64x64] = x265_pixel_ssd_64x64_sse4;
+ p.sse_sp[LUMA_16x4] = x265_pixel_ssd_sp_16x4_sse4;
+ p.sse_sp[LUMA_16x8] = x265_pixel_ssd_sp_16x8_sse4;
+ p.sse_sp[LUMA_16x12] = x265_pixel_ssd_sp_16x12_sse4;
+ p.sse_sp[LUMA_16x16] = x265_pixel_ssd_sp_16x16_sse4;
+ p.sse_sp[LUMA_16x32] = x265_pixel_ssd_sp_16x32_sse4;
+ p.sse_sp[LUMA_16x64] = x265_pixel_ssd_sp_16x64_sse4;
+
CHROMA_PIXELSUB_PS(_sse4);
CHROMA_FILTERS(_sse4);
diff -r e17784926dd2 -r b4be37816bb4 source/common/x86/pixel-a.asm
--- a/source/common/x86/pixel-a.asm Tue Nov 26 13:31:22 2013 +0530
+++ b/source/common/x86/pixel-a.asm Tue Nov 26 17:46:24 2013 +0530
@@ -988,6 +988,261 @@
RET
;-----------------------------------------------------------------------------
+; int pixel_ssd_sp_16x4( int16_t *, intptr_t, uint8_t *, intptr_t )
+;-----------------------------------------------------------------------------
+INIT_XMM sse4
+cglobal pixel_ssd_sp_16x4, 4, 6, 8, src1, stride1, src2, stride2
+
+ pxor m6, m6
+ pxor m7, m7
+ add r1, r1
+ lea r4, [r1 * 3]
+ lea r5, [r3 * 3]
+
+ movu m0, [r0]
+ movu m1, [r0 + 16]
+ movu m3, [r2]
+ pmovzxbw m2, m3
+ punpckhbw m3, m6
+
+ psubw m0, m2
+ psubw m1, m3
+
+ movu m4, [r0 + r1]
+ movu m5, [r0 + r1 +16]
+ movu m3, [r2 + r3]
+ pmovzxbw m2, m3
+ punpckhbw m3, m6
+
+ psubw m4, m2
+ psubw m5, m3
+
+ pmaddwd m0, m0
+ pmaddwd m1, m1
+ pmaddwd m4, m4
+ pmaddwd m5, m5
+
+ paddd m0, m1
+ paddd m4, m5
+ paddd m4, m0
+ paddd m7, m4
+
+ movu m0, [r0 + 2 * r1]
+ movu m1, [r0 + 2 * r1 + 16]
+ movu m3, [r2 + 2 * r3]
+ pmovzxbw m2, m3
+ punpckhbw m3, m6
+
+ psubw m0, m2
+ psubw m1, m3
+
+ movu m4, [r0 + r4]
+ movu m5, [r0 + r4 + 16]
+ movu m3, [r2 + r5]
+ pmovzxbw m2, m3
+ punpckhbw m3, m6
+
+ psubw m4, m2
+ psubw m5, m3
+
+ pmaddwd m0, m0
+ pmaddwd m1, m1
+ pmaddwd m4, m4
+ pmaddwd m5, m5
+
+ paddd m0, m1
+ paddd m4, m5
+ paddd m4, m0
+ paddd m7, m4
+
+ HADDD m7, m1
+ movd eax, m7
+
+ RET
+
+%macro PIXEL_SSD_SP_16x4 0
+ movu m0, [r0]
+ movu m1, [r0 + 16]
+ movu m3, [r2]
+ pmovzxbw m2, m3
+ punpckhbw m3, m6
+
+ psubw m0, m2
+ psubw m1, m3
+
+ movu m4, [r0 + r1]
+ movu m5, [r0 + r1 +16]
+ movu m3, [r2 + r3]
+ pmovzxbw m2, m3
+ punpckhbw m3, m6
+
+ psubw m4, m2
+ psubw m5, m3
+
+ pmaddwd m0, m0
+ pmaddwd m1, m1
+ pmaddwd m4, m4
+ pmaddwd m5, m5
+
+ paddd m0, m1
+ paddd m4, m5
+ paddd m4, m0
+ paddd m7, m4
+
+ movu m0, [r0 + 2 * r1]
+ movu m1, [r0 + 2 * r1 + 16]
+ movu m3, [r2 + 2 * r3]
+ pmovzxbw m2, m3
+ punpckhbw m3, m6
+
+ psubw m0, m2
+ psubw m1, m3
+
+ lea r0, [r0 + 2 * r1]
+ lea r2, [r2 + 2 * r3]
+ movu m4, [r0 + r1]
+ movu m5, [r0 + r1 + 16]
+ movu m3, [r2 + r3]
+ pmovzxbw m2, m3
+ punpckhbw m3, m6
+
+ psubw m4, m2
+ psubw m5, m3
+
+ pmaddwd m0, m0
+ pmaddwd m1, m1
+ pmaddwd m4, m4
+ pmaddwd m5, m5
+
+ paddd m0, m1
+ paddd m4, m5
+ paddd m4, m0
+ paddd m7, m4
+%endmacro
+
+
+;-----------------------------------------------------------------------------
+; int pixel_ssd_sp_16x8( int16_t *, intptr_t, uint8_t *, intptr_t )
+;-----------------------------------------------------------------------------
+INIT_XMM sse4
+cglobal pixel_ssd_sp_16x8, 4, 4, 8, src1, stride1, src2, stride2
+
+ pxor m6, m6
+ pxor m7, m7
+ add r1, r1
+ PIXEL_SSD_SP_16x4
+ lea r0, [r0 + 2 * r1]
+ lea r2, [r2 + 2 * r3]
+ PIXEL_SSD_SP_16x4
+ HADDD m7, m1
+ movd eax, m7
+ RET
+
+;-----------------------------------------------------------------------------
+; int pixel_ssd_sp_16x12( int16_t *, intptr_t, uint8_t *, intptr_t )
+;-----------------------------------------------------------------------------
+INIT_XMM sse4
+cglobal pixel_ssd_sp_16x12, 4, 6, 8, src1, stride1, src2, stride2
+
+ pxor m6, m6
+ pxor m7, m7
+ add r1, r1
+ lea r4, [r1 * 2]
+ lea r5, [r3 * 2]
+ PIXEL_SSD_SP_16x4
+ lea r0, [r0 + r4]
+ lea r2, [r2 + r5]
+ PIXEL_SSD_SP_16x4
+ lea r0, [r0 + r4]
+ lea r2, [r2 + r5]
+ PIXEL_SSD_SP_16x4
+ HADDD m7, m1
+ movd eax, m7
+ RET
+
+;-----------------------------------------------------------------------------
+; int pixel_ssd_sp_16x16( int16_t *, intptr_t, uint8_t *, intptr_t )
+;-----------------------------------------------------------------------------
+INIT_XMM sse4
+cglobal pixel_ssd_sp_16x16, 4, 6, 8, src1, stride1, src2, stride2
+
+ pxor m6, m6
+ pxor m7, m7
+ add r1, r1
+ lea r4, [r1 * 2]
+ lea r5, [r3 * 2]
+ PIXEL_SSD_SP_16x4
+ lea r0, [r0 + r4]
+ lea r2, [r2 + r5]
+ PIXEL_SSD_SP_16x4
+ lea r0, [r0 + r4]
+ lea r2, [r2 + r5]
+ PIXEL_SSD_SP_16x4
+ lea r0, [r0 + r4]
+ lea r2, [r2 + r5]
+ PIXEL_SSD_SP_16x4
+ HADDD m7, m1
+ movd eax, m7
+ RET
+
+cglobal pixel_ssd_sp_16x16_internal
+ PIXEL_SSD_SP_16x4
+ lea r0, [r0 + r4]
+ lea r2, [r2 + 2 * r3]
+ PIXEL_SSD_SP_16x4
+ lea r0, [r0 + r4]
+ lea r2, [r2 + 2 * r3]
+ PIXEL_SSD_SP_16x4
+ lea r0, [r0 + r4]
+ lea r2, [r2 + 2 * r3]
+ PIXEL_SSD_SP_16x4
+ ret
+
+;-----------------------------------------------------------------------------
+; int pixel_ssd_sp_16x32( int16_t *, intptr_t, uint8_t *, intptr_t )
+;-----------------------------------------------------------------------------
+INIT_XMM sse4
+cglobal pixel_ssd_sp_16x32, 4, 5, 8, src1, stride1, src2, stride2
+
+ pxor m6, m6
+ pxor m7, m7
+ add r1, r1
+ lea r4, [r1 * 2]
+ call pixel_ssd_sp_16x16_internal
+ lea r0, [r0 + r4]
+ lea r2, [r2 + 2 * r3]
+ call pixel_ssd_sp_16x16_internal
+ HADDD m7, m1
+ movd eax, m7
+ RET
+
+;-----------------------------------------------------------------------------
+; int pixel_ssd_sp_16x64( int16_t *, intptr_t, uint8_t *, intptr_t )
+;-----------------------------------------------------------------------------
+INIT_XMM sse4
+cglobal pixel_ssd_sp_16x64, 4, 6, 8, src1, stride1, src2, stride2
+
+ pxor m6, m6
+ pxor m7, m7
+ add r1, r1
+ lea r4, [r1 * 2]
+ lea r5, [r3 * 2]
+ call pixel_ssd_sp_16x16_internal
+ lea r0, [r0 + r4]
+ lea r2, [r2 + r5]
+ call pixel_ssd_sp_16x16_internal
+ lea r0, [r0 + r4]
+ lea r2, [r2 + r5]
+ call pixel_ssd_sp_16x16_internal
+ lea r0, [r0 + r4]
+ lea r2, [r2 + r5]
+ call pixel_ssd_sp_16x16_internal
+
+ HADDD m7, m1
+ movd eax, m7
+ RET
+
+;-----------------------------------------------------------------------------
; void pixel_ssd_nv12_core( uint16_t *pixuv1, intptr_t stride1, uint16_t *pixuv2, intptr_t stride2,
; int width, int height, uint64_t *ssd_u, uint64_t *ssd_v )
;
diff -r e17784926dd2 -r b4be37816bb4 source/common/x86/pixel.h
--- a/source/common/x86/pixel.h Tue Nov 26 13:31:22 2013 +0530
+++ b/source/common/x86/pixel.h Tue Nov 26 17:46:24 2013 +0530
@@ -391,4 +391,11 @@
int x265_pixel_ssd_64x48_sse4(pixel *, intptr_t, pixel *, intptr_t);
int x265_pixel_ssd_64x64_sse4(pixel *, intptr_t, pixel *, intptr_t);
+int x265_pixel_ssd_sp_16x4_sse4(int16_t *, intptr_t, pixel *, intptr_t);
+int x265_pixel_ssd_sp_16x8_sse4(int16_t *, intptr_t, pixel *, intptr_t);
+int x265_pixel_ssd_sp_16x12_sse4(int16_t *, intptr_t, pixel *, intptr_t);
+int x265_pixel_ssd_sp_16x16_sse4(int16_t *, intptr_t, pixel *, intptr_t);
+int x265_pixel_ssd_sp_16x32_sse4(int16_t *, intptr_t, pixel *, intptr_t);
+int x265_pixel_ssd_sp_16x64_sse4(int16_t *, intptr_t, pixel *, intptr_t);
+
#endif // ifndef X265_I386_PIXEL_H
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