[x265] [PATCH] asm: assembly code for pixel_sse_ss_64xN

[yuvaraj at multicorewareinc.com]

# HG changeset patch
# User Yuvaraj Venkatesh <yuvaraj at multicorewareinc.com>
# Date 1385475001 -19800
#      Tue Nov 26 19:40:01 2013 +0530
# Node ID 60c8dbd19c7e38d6e425b8246a3d8f4b10e3b53b
# Parent  e27cac92aff9c93f911276fedd87c5e4f77ca386
asm: assembly code for pixel_sse_ss_64xN

diff -r e27cac92aff9 -r 60c8dbd19c7e source/common/x86/asm-primitives.cpp
--- a/source/common/x86/asm-primitives.cpp	Tue Nov 26 19:35:56 2013 +0530
+++ b/source/common/x86/asm-primitives.cpp	Tue Nov 26 19:40:01 2013 +0530
@@ -110,6 +110,10 @@
     p.sse_ss[LUMA_32x32]   = x265_pixel_ssd_ss_32x32_ ## cpu; \
     p.sse_ss[LUMA_32x64]   = x265_pixel_ssd_ss_32x64_ ## cpu; \
     p.sse_ss[LUMA_48x64]   = x265_pixel_ssd_ss_48x64_ ## cpu; \
+    p.sse_ss[LUMA_64x16]   = x265_pixel_ssd_ss_64x16_ ## cpu; \
+    p.sse_ss[LUMA_64x32]   = x265_pixel_ssd_ss_64x32_ ## cpu; \
+    p.sse_ss[LUMA_64x48]   = x265_pixel_ssd_ss_64x48_ ## cpu; \
+    p.sse_ss[LUMA_64x64]   = x265_pixel_ssd_ss_64x64_ ## cpu;
 
 #define SA8D_INTER_FROM_BLOCK(cpu) \
     p.sa8d_inter[LUMA_4x8]  = x265_pixel_satd_4x8_ ## cpu; \
diff -r e27cac92aff9 -r 60c8dbd19c7e source/common/x86/pixel-a.asm
--- a/source/common/x86/pixel-a.asm	Tue Nov 26 19:35:56 2013 +0530
+++ b/source/common/x86/pixel-a.asm	Tue Nov 26 19:40:01 2013 +0530
@@ -595,24 +595,132 @@
     RET
 %endmacro
 
+%macro SSD_SS_64 1
+cglobal pixel_ssd_ss_64x%1, 4,7,6
+    FIX_STRIDES r1, r3
+    mov    r4d, %1/2
+    pxor    m0, m0
+.loop
+    mova    m1, [r0]
+    movu    m2, [r2]
+    psubw   m1, m2
+    pmaddwd m1, m1
+    paddd   m0, m1
+    mova    m1, [r0 + 16]
+    movu    m2, [r2 + 16]
+    psubw   m1, m2
+    pmaddwd m1, m1
+    paddd   m0, m1
+    mova    m1, [r0 + 32]
+    movu    m2, [r2 + 32]
+    psubw   m1, m2
+    pmaddwd m1, m1
+    paddd   m0, m1
+    mova    m1, [r0 + 48]
+    movu    m2, [r2 + 48]
+    psubw   m1, m2
+    pmaddwd m1, m1
+    paddd   m0, m1
+    mova    m1, [r0 + 64]
+    movu    m2, [r2 + 64]
+    psubw   m1, m2
+    pmaddwd m1, m1
+    paddd   m0, m1
+    mova    m1, [r0 + 80]
+    movu    m2, [r2 + 80]
+    psubw   m1, m2
+    pmaddwd m1, m1
+    paddd   m0, m1
+    mova    m1, [r0 + 96]
+    movu    m2, [r2 + 96]
+    psubw   m1, m2
+    pmaddwd m1, m1
+    paddd   m0, m1
+    mova    m1, [r0 + 112]
+    movu    m2, [r2 + 112]
+    psubw   m1, m2
+    pmaddwd m1, m1
+    paddd   m0, m1
+    lea     r0, [r0 + 2*r1]
+    lea     r2, [r2 + 2*r3]
+    mova    m1, [r0]
+    movu    m2, [r2]
+    psubw   m1, m2
+    pmaddwd m1, m1
+    paddd   m0, m1
+    mova    m1, [r0 + 16]
+    movu    m2, [r2 + 16]
+    psubw   m1, m2
+    pmaddwd m1, m1
+    paddd   m0, m1
+    mova    m1, [r0 + 32]
+    movu    m2, [r2 + 32]
+    psubw   m1, m2
+    pmaddwd m1, m1
+    paddd   m0, m1
+    mova    m1, [r0 + 48]
+    movu    m2, [r2 + 48]
+    psubw   m1, m2
+    pmaddwd m1, m1
+    paddd   m0, m1
+    mova    m1, [r0 + 64]
+    movu    m2, [r2 + 64]
+    psubw   m1, m2
+    pmaddwd m1, m1
+    paddd   m0, m1
+    mova    m1, [r0 + 80]
+    movu    m2, [r2 + 80]
+    psubw   m1, m2
+    pmaddwd m1, m1
+    paddd   m0, m1
+    mova    m1, [r0 + 96]
+    movu    m2, [r2 + 96]
+    psubw   m1, m2
+    pmaddwd m1, m1
+    paddd   m0, m1
+    mova    m1, [r0 + 112]
+    movu    m2, [r2 + 112]
+    psubw   m1, m2
+    pmaddwd m1, m1
+    paddd   m0, m1
+    lea     r0, [r0 + 2*r1]
+    lea     r2, [r2 + 2*r3]
+    dec     r4d
+    jnz .loop
+    phaddd    m0, m0
+    phaddd    m0, m0
+    movd     eax, m0
+    RET
+%endmacro
+
+%macro SSD_SS_64xN 0
+SSD_SS_64 16
+SSD_SS_64 32
+SSD_SS_64 48
+SSD_SS_64 64
+%endmacro
+
 INIT_XMM sse2
 SSD_SS_ONE
 SSD_SS_12x16
 SSD_SS_24
 SSD_SS_32xN
 SSD_SS_48
+SSD_SS_64xN
 INIT_XMM sse4
 SSD_SS_ONE
 SSD_SS_12x16
 SSD_SS_24
 SSD_SS_32xN
 SSD_SS_48
+SSD_SS_64xN
 INIT_XMM avx
 SSD_SS_ONE
 SSD_SS_12x16
 SSD_SS_24
 SSD_SS_32xN
 SSD_SS_48
+SSD_SS_64xN
 %endif ; !HIGH_BIT_DEPTH
 
 %if HIGH_BIT_DEPTH == 0