[x265] [PATCH] asm: code for pixel_sse_sp_8xN
murugan at multicorewareinc.com
murugan at multicorewareinc.com
Wed Nov 27 14:41:41 CET 2013
# HG changeset patch
# User Murugan Vairavel <murugan at multicorewareinc.com>
# Date 1385559693 -19800
# Wed Nov 27 19:11:33 2013 +0530
# Branch stable
# Node ID f8eef9dd7e408748e505a7a7d3253b32cb6702bd
# Parent 7078582cea0ba56fbaf24dc9041f0d1aa66ac46a
asm: code for pixel_sse_sp_8xN
diff -r 7078582cea0b -r f8eef9dd7e40 source/common/x86/asm-primitives.cpp
--- a/source/common/x86/asm-primitives.cpp Wed Nov 27 16:23:05 2013 +0530
+++ b/source/common/x86/asm-primitives.cpp Wed Nov 27 19:11:33 2013 +0530
@@ -641,6 +641,10 @@
p.sse_pp[LUMA_64x48] = x265_pixel_ssd_64x48_sse4;
p.sse_pp[LUMA_64x64] = x265_pixel_ssd_64x64_sse4;
+ p.sse_sp[LUMA_8x4] = x265_pixel_ssd_sp_8x4_sse4;
+ p.sse_sp[LUMA_8x8] = x265_pixel_ssd_sp_8x8_sse4;
+ p.sse_sp[LUMA_8x16] = x265_pixel_ssd_sp_8x16_sse4;
+ p.sse_sp[LUMA_8x32] = x265_pixel_ssd_sp_8x32_sse4;
p.sse_sp[LUMA_16x4] = x265_pixel_ssd_sp_16x4_sse4;
p.sse_sp[LUMA_16x8] = x265_pixel_ssd_sp_16x8_sse4;
p.sse_sp[LUMA_16x12] = x265_pixel_ssd_sp_16x12_sse4;
diff -r 7078582cea0b -r f8eef9dd7e40 source/common/x86/pixel-a.asm
--- a/source/common/x86/pixel-a.asm Wed Nov 27 16:23:05 2013 +0530
+++ b/source/common/x86/pixel-a.asm Wed Nov 27 19:11:33 2013 +0530
@@ -1216,6 +1216,127 @@
; int pixel_ssd_sp ( int16_t *, intptr_t, uint8_t *, intptr_t )
;-----------------------------------------------------------------------------
+cglobal pixel_ssd_sp_8x4_internal
+ movu m0, [r0]
+ movu m1, [r0 + r1]
+ movh m2, [r2]
+ movh m3, [r2 + r3]
+ pmovzxbw m2, m2
+ pmovzxbw m3, m3
+
+ psubw m0, m2
+ psubw m1, m3
+
+ movu m4, [r0 + 2 * r1]
+ movu m5, [r0 + r4]
+ movh m2, [r2 + 2 * r3]
+ movh m3, [r2 + r5]
+ pmovzxbw m2, m2
+ pmovzxbw m3, m3
+
+ psubw m4, m2
+ psubw m5, m3
+
+ pmaddwd m0, m0
+ pmaddwd m1, m1
+ pmaddwd m4, m4
+ pmaddwd m5, m5
+
+ paddd m0, m1
+ paddd m4, m5
+ paddd m4, m0
+ paddd m7, m4
+ ret
+
+;-----------------------------------------------------------------------------
+; int pixel_ssd_sp_8x4( int16_t *, intptr_t, uint8_t *, intptr_t )
+;-----------------------------------------------------------------------------
+INIT_XMM sse4
+cglobal pixel_ssd_sp_8x4, 4, 6, 8, src1, stride1, src2, stride2
+ pxor m7, m7
+ add r1, r1
+ lea r4, [r1 * 3]
+ lea r5, [r3 * 3]
+ call pixel_ssd_sp_8x4_internal
+ HADDD m7, m1
+ movd eax, m7
+ RET
+
+;-----------------------------------------------------------------------------
+; int pixel_ssd_sp_8x8( int16_t *, intptr_t, uint8_t *, intptr_t )
+;-----------------------------------------------------------------------------
+INIT_XMM sse4
+cglobal pixel_ssd_sp_8x8, 4, 6, 8, src1, stride1, src2, stride2
+ pxor m7, m7
+ add r1, r1
+ lea r4, [r1 * 3]
+ lea r5, [r3 * 3]
+ call pixel_ssd_sp_8x4_internal
+ lea r0, [r0 + 4 * r1]
+ lea r2, [r2 + 4 * r3]
+ call pixel_ssd_sp_8x4_internal
+ HADDD m7, m1
+ movd eax, m7
+ RET
+
+;-----------------------------------------------------------------------------
+; int pixel_ssd_sp_8x16( int16_t *, intptr_t, uint8_t *, intptr_t )
+;-----------------------------------------------------------------------------
+INIT_XMM sse4
+cglobal pixel_ssd_sp_8x16, 4, 6, 8, src1, stride1, src2, stride2
+ pxor m7, m7
+ add r1, r1
+ lea r4, [r1 * 3]
+ lea r5, [r3 * 3]
+ call pixel_ssd_sp_8x4_internal
+ lea r0, [r0 + 4 * r1]
+ lea r2, [r2 + 4 * r3]
+ call pixel_ssd_sp_8x4_internal
+ lea r0, [r0 + 4 * r1]
+ lea r2, [r2 + 4 * r3]
+ call pixel_ssd_sp_8x4_internal
+ lea r0, [r0 + 4 * r1]
+ lea r2, [r2 + 4 * r3]
+ call pixel_ssd_sp_8x4_internal
+ HADDD m7, m1
+ movd eax, m7
+ RET
+
+;-----------------------------------------------------------------------------
+; int pixel_ssd_sp_8x32( int16_t *, intptr_t, uint8_t *, intptr_t )
+;-----------------------------------------------------------------------------
+INIT_XMM sse4
+cglobal pixel_ssd_sp_8x32, 4, 6, 8, src1, stride1, src2, stride2
+ pxor m7, m7
+ add r1, r1
+ lea r4, [r1 * 3]
+ lea r5, [r3 * 3]
+ call pixel_ssd_sp_8x4_internal
+ lea r0, [r0 + 4 * r1]
+ lea r2, [r2 + 4 * r3]
+ call pixel_ssd_sp_8x4_internal
+ lea r0, [r0 + 4 * r1]
+ lea r2, [r2 + 4 * r3]
+ call pixel_ssd_sp_8x4_internal
+ lea r0, [r0 + 4 * r1]
+ lea r2, [r2 + 4 * r3]
+ call pixel_ssd_sp_8x4_internal
+ lea r0, [r0 + 4 * r1]
+ lea r2, [r2 + 4 * r3]
+ call pixel_ssd_sp_8x4_internal
+ lea r0, [r0 + 4 * r1]
+ lea r2, [r2 + 4 * r3]
+ call pixel_ssd_sp_8x4_internal
+ lea r0, [r0 + 4 * r1]
+ lea r2, [r2 + 4 * r3]
+ call pixel_ssd_sp_8x4_internal
+ lea r0, [r0 + 4 * r1]
+ lea r2, [r2 + 4 * r3]
+ call pixel_ssd_sp_8x4_internal
+ HADDD m7, m1
+ movd eax, m7
+ RET
+
%macro PIXEL_SSD_SP_16x4 0
movu m0, [r0]
movu m1, [r0 + 16]
diff -r 7078582cea0b -r f8eef9dd7e40 source/common/x86/pixel.h
--- a/source/common/x86/pixel.h Wed Nov 27 16:23:05 2013 +0530
+++ b/source/common/x86/pixel.h Wed Nov 27 19:11:33 2013 +0530
@@ -401,6 +401,10 @@
void x265_weight_pp_sse4(pixel *src, pixel *dst, intptr_t srcStride, intptr_t dstStride, int width, int height, int w0, int round, int shift, int offset);
void x265_weight_sp_sse4(int16_t *src, pixel *dst, intptr_t srcStride, intptr_t dstStride, int width, int height, int w0, int round, int shift, int offset);
+int x265_pixel_ssd_sp_8x4_sse4(int16_t *, intptr_t, pixel *, intptr_t);
+int x265_pixel_ssd_sp_8x8_sse4(int16_t *, intptr_t, pixel *, intptr_t);
+int x265_pixel_ssd_sp_8x16_sse4(int16_t *, intptr_t, pixel *, intptr_t);
+int x265_pixel_ssd_sp_8x32_sse4(int16_t *, intptr_t, pixel *, intptr_t);
int x265_pixel_ssd_sp_16x4_sse4(int16_t *, intptr_t, pixel *, intptr_t);
int x265_pixel_ssd_sp_16x8_sse4(int16_t *, intptr_t, pixel *, intptr_t);
int x265_pixel_ssd_sp_16x12_sse4(int16_t *, intptr_t, pixel *, intptr_t);
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