[x265] [PATCH Review Only] asm: assembly code for pixel_sad_32x64

[dnyaneshwar at multicorewareinc.com]

# HG changeset patch
# User Dnyaneshwar Gorade <dnyaneshwar at multicorewareinc.com>
# Date 1383051530 -19800
#      Tue Oct 29 18:28:50 2013 +0530
# Node ID fd262a178291ff7c0732017f2d5ff138559d7fa9
# Parent  235bbc4600b8592c968e2658a46533ee032b69fd
asm: assembly code for pixel_sad_32x64

diff -r 235bbc4600b8 -r fd262a178291 source/common/x86/asm-primitives.cpp
--- a/source/common/x86/asm-primitives.cpp	Tue Oct 29 18:25:54 2013 +0530
+++ b/source/common/x86/asm-primitives.cpp	Tue Oct 29 18:28:50 2013 +0530
@@ -242,6 +242,7 @@
         p.sad[LUMA_32x16]  = x265_pixel_sad_32x16_sse2;
         p.sad[LUMA_32x24]  = x265_pixel_sad_32x24_sse2;
         p.sad[LUMA_32x32]  = x265_pixel_sad_32x32_sse2;
+        p.sad[LUMA_32x64]  = x265_pixel_sad_32x64_sse2;
 
         ASSGN_SSE(sse2);
         INIT2(sad, _sse2);
diff -r 235bbc4600b8 -r fd262a178291 source/common/x86/sad-a.asm
--- a/source/common/x86/sad-a.asm	Tue Oct 29 18:25:54 2013 +0530
+++ b/source/common/x86/sad-a.asm	Tue Oct 29 18:28:50 2013 +0530
@@ -542,6 +542,64 @@
     movd    eax, m0
     RET
 
+;-----------------------------------------------------------------------------
+; int pixel_sad_32x64( uint8_t *, intptr_t, uint8_t *, intptr_t )
+;-----------------------------------------------------------------------------
+cglobal pixel_sad_32x64, 4,4,3
+    pxor  m0,  m0
+
+    PROCESS_SAD_32x4
+    PROCESS_SAD_32x4
+    PROCESS_SAD_32x4
+    PROCESS_SAD_32x4
+    PROCESS_SAD_32x4
+    PROCESS_SAD_32x4
+    PROCESS_SAD_32x4
+    PROCESS_SAD_32x4
+    PROCESS_SAD_32x4
+    PROCESS_SAD_32x4
+    PROCESS_SAD_32x4
+    PROCESS_SAD_32x4
+    PROCESS_SAD_32x4
+    PROCESS_SAD_32x4
+    PROCESS_SAD_32x4
+
+    movu    m1,  [r2]
+    movu    m2,  [r2 + 16]
+    psadbw  m1,  [r0]
+    psadbw  m2,  [r0 + 16]
+    paddd   m1,  m2
+    paddd   m0,  m1
+    lea     r2,  [r2 + r3]
+    lea     r0,  [r0 + r1]
+    movu    m1,  [r2]
+    movu    m2,  [r2 + 16]
+    psadbw  m1,  [r0]
+    psadbw  m2,  [r0 + 16]
+    paddd   m1,  m2
+    paddd   m0,  m1
+    lea     r2,  [r2 + r3]
+    lea     r0,  [r0 + r1]
+    movu    m1,  [r2]
+    movu    m2,  [r2 + 16]
+    psadbw  m1,  [r0]
+    psadbw  m2,  [r0 + 16]
+    paddd   m1,  m2
+    paddd   m0,  m1
+    lea     r2,  [r2 + r3]
+    lea     r0,  [r0 + r1]
+    movu    m1,  [r2]
+    movu    m2,  [r2 + 16]
+    psadbw  m1,  [r0]
+    psadbw  m2,  [r0 + 16]
+    paddd   m1,  m2
+    paddd   m0,  m1
+
+    movhlps m1,  m0
+    paddd   m0,  m1
+    movd    eax, m0
+    RET
+
 %endmacro
 
 INIT_XMM sse2