[x265] [PATCH] asm: filter_vpp, filter_vps for 16x64 in avx2

[Divya Manivannan]

# HG changeset patch
# User Divya Manivannan <divya at multicorewareinc.com>
# Date 1430294882 -19800
#      Wed Apr 29 13:38:02 2015 +0530
# Node ID 277c08afe66dbe1db06acd62087b829a18395ca1
# Parent  41a94b5fe6a8b2d0d964955971377731a48439ac
asm: filter_vpp, filter_vps for 16x64 in avx2

filter_vpp[16x64]: 4281c->3767c
filter_vps[16x64]: 4295c->3396c

diff -r 41a94b5fe6a8 -r 277c08afe66d source/common/x86/asm-primitives.cpp
--- a/source/common/x86/asm-primitives.cpp	Wed Apr 29 11:46:53 2015 +0530
+++ b/source/common/x86/asm-primitives.cpp	Wed Apr 29 13:38:02 2015 +0530
@@ -2532,6 +2532,7 @@
         p.chroma[X265_CSP_I422].pu[CHROMA_422_8x4].filter_vps = x265_interp_4tap_vert_ps_8x4_avx2;
         p.chroma[X265_CSP_I422].pu[CHROMA_422_16x8].filter_vps = x265_interp_4tap_vert_ps_16x8_avx2;
         p.chroma[X265_CSP_I422].pu[CHROMA_422_32x16].filter_vps = x265_interp_4tap_vert_ps_32x16_avx2;
+        p.chroma[X265_CSP_I422].pu[CHROMA_422_16x64].filter_vps = x265_interp_4tap_vert_ps_16x64_avx2;
 
         //i444 for chroma_vps
         p.chroma[X265_CSP_I444].pu[LUMA_4x4].filter_vps = x265_interp_4tap_vert_ps_4x4_avx2;
@@ -2552,6 +2553,7 @@
         p.chroma[X265_CSP_I444].pu[LUMA_24x32].filter_vps = x265_interp_4tap_vert_ps_24x32_avx2;
         p.chroma[X265_CSP_I444].pu[LUMA_32x8].filter_vps = x265_interp_4tap_vert_ps_32x8_avx2;
         p.chroma[X265_CSP_I444].pu[LUMA_8x32].filter_vps = x265_interp_4tap_vert_ps_8x32_avx2;
+        p.chroma[X265_CSP_I444].pu[LUMA_16x64].filter_vps = x265_interp_4tap_vert_ps_16x64_avx2;
 
         //i422 for chroma_vpp
         p.chroma[X265_CSP_I422].pu[CHROMA_422_4x8].filter_vpp = x265_interp_4tap_vert_pp_4x8_avx2;
@@ -2567,6 +2569,7 @@
         p.chroma[X265_CSP_I422].pu[CHROMA_422_8x4].filter_vpp = x265_interp_4tap_vert_pp_8x4_avx2;
         p.chroma[X265_CSP_I422].pu[CHROMA_422_16x8].filter_vpp = x265_interp_4tap_vert_pp_16x8_avx2;
         p.chroma[X265_CSP_I422].pu[CHROMA_422_32x16].filter_vpp = x265_interp_4tap_vert_pp_32x16_avx2;
+        p.chroma[X265_CSP_I422].pu[CHROMA_422_16x64].filter_vpp = x265_interp_4tap_vert_pp_16x64_avx2;
 
         //i444 for chroma_vpp
         p.chroma[X265_CSP_I444].pu[LUMA_4x4].filter_vpp = x265_interp_4tap_vert_pp_4x4_avx2;
@@ -2587,6 +2590,7 @@
         p.chroma[X265_CSP_I444].pu[LUMA_24x32].filter_vpp = x265_interp_4tap_vert_pp_24x32_avx2;
         p.chroma[X265_CSP_I444].pu[LUMA_32x8].filter_vpp = x265_interp_4tap_vert_pp_32x8_avx2;
         p.chroma[X265_CSP_I444].pu[LUMA_8x32].filter_vpp = x265_interp_4tap_vert_pp_8x32_avx2;
+        p.chroma[X265_CSP_I444].pu[LUMA_16x64].filter_vpp = x265_interp_4tap_vert_pp_16x64_avx2;
 
         if (cpuMask & X265_CPU_BMI2)
             p.scanPosLast = x265_scanPosLast_avx2_bmi2;
diff -r 41a94b5fe6a8 -r 277c08afe66d source/common/x86/ipfilter8.asm
--- a/source/common/x86/ipfilter8.asm	Wed Apr 29 11:46:53 2015 +0530
+++ b/source/common/x86/ipfilter8.asm	Wed Apr 29 13:38:02 2015 +0530
@@ -6714,10 +6714,10 @@
     FILTER_VER_CHROMA_AVX2_16x12 pp
     FILTER_VER_CHROMA_AVX2_16x12 ps
 
-%macro FILTER_VER_CHROMA_AVX2_16x32 1
-INIT_YMM avx2
-%if ARCH_X86_64 == 1
-cglobal interp_4tap_vert_%1_16x32, 4, 8, 8
+%macro FILTER_VER_CHROMA_AVX2_16xN 2
+%if ARCH_X86_64 == 1
+INIT_YMM avx2
+cglobal interp_4tap_vert_%1_16x%2, 4, 8, 8
     mov             r4d, r4m
     shl             r4d, 6
 
@@ -6737,7 +6737,7 @@
     mova            m7, [pw_2000]
 %endif
     lea             r6, [r3 * 3]
-    mov             r7d, 2
+    mov             r7d, %2 / 16
 .loopH:
     movu            xm0, [r0]
     vinserti128     m0, m0, [r0 + r1 * 2], 1
@@ -7004,8 +7004,10 @@
 %endif
 %endmacro
 
-    FILTER_VER_CHROMA_AVX2_16x32 pp
-    FILTER_VER_CHROMA_AVX2_16x32 ps
+    FILTER_VER_CHROMA_AVX2_16xN pp, 32
+    FILTER_VER_CHROMA_AVX2_16xN ps, 32
+    FILTER_VER_CHROMA_AVX2_16xN pp, 64
+    FILTER_VER_CHROMA_AVX2_16xN ps, 64
 
 %macro FILTER_VER_CHROMA_AVX2_24x32 1
 INIT_YMM avx2