[x265] [PATCH] asm: filter_vpp, filter_vps for 8x64 in avx2

[Divya Manivannan]

# HG changeset patch
# User Divya Manivannan <divya at multicorewareinc.com>
# Date 1430300039 -19800
#      Wed Apr 29 15:03:59 2015 +0530
# Node ID 9b2dd8a535bc5216ea12e3d1abde32019775b8fb
# Parent  277c08afe66dbe1db06acd62087b829a18395ca1
asm: filter_vpp, filter_vps for 8x64 in avx2

filter_vpp[8x64]: 2083c->1820c
filter_vps[8x64]: 2215c->1722c

diff -r 277c08afe66d -r 9b2dd8a535bc source/common/x86/asm-primitives.cpp
--- a/source/common/x86/asm-primitives.cpp	Wed Apr 29 13:38:02 2015 +0530
+++ b/source/common/x86/asm-primitives.cpp	Wed Apr 29 15:03:59 2015 +0530
@@ -2533,6 +2533,7 @@
         p.chroma[X265_CSP_I422].pu[CHROMA_422_16x8].filter_vps = x265_interp_4tap_vert_ps_16x8_avx2;
         p.chroma[X265_CSP_I422].pu[CHROMA_422_32x16].filter_vps = x265_interp_4tap_vert_ps_32x16_avx2;
         p.chroma[X265_CSP_I422].pu[CHROMA_422_16x64].filter_vps = x265_interp_4tap_vert_ps_16x64_avx2;
+        p.chroma[X265_CSP_I422].pu[CHROMA_422_8x64].filter_vps = x265_interp_4tap_vert_ps_8x64_avx2;
 
         //i444 for chroma_vps
         p.chroma[X265_CSP_I444].pu[LUMA_4x4].filter_vps = x265_interp_4tap_vert_ps_4x4_avx2;
@@ -2570,6 +2571,7 @@
         p.chroma[X265_CSP_I422].pu[CHROMA_422_16x8].filter_vpp = x265_interp_4tap_vert_pp_16x8_avx2;
         p.chroma[X265_CSP_I422].pu[CHROMA_422_32x16].filter_vpp = x265_interp_4tap_vert_pp_32x16_avx2;
         p.chroma[X265_CSP_I422].pu[CHROMA_422_16x64].filter_vpp = x265_interp_4tap_vert_pp_16x64_avx2;
+        p.chroma[X265_CSP_I422].pu[CHROMA_422_8x64].filter_vpp = x265_interp_4tap_vert_pp_8x64_avx2;
 
         //i444 for chroma_vpp
         p.chroma[X265_CSP_I444].pu[LUMA_4x4].filter_vpp = x265_interp_4tap_vert_pp_4x4_avx2;
diff -r 277c08afe66d -r 9b2dd8a535bc source/common/x86/ipfilter8.asm
--- a/source/common/x86/ipfilter8.asm	Wed Apr 29 13:38:02 2015 +0530
+++ b/source/common/x86/ipfilter8.asm	Wed Apr 29 15:03:59 2015 +0530
@@ -5556,9 +5556,9 @@
     FILTER_VER_CHROMA_AVX2_8x16 pp
     FILTER_VER_CHROMA_AVX2_8x16 ps
 
-%macro FILTER_VER_CHROMA_AVX2_8x32 1
-INIT_YMM avx2
-cglobal interp_4tap_vert_%1_8x32, 4, 7, 8
+%macro FILTER_VER_CHROMA_AVX2_8xN 2
+INIT_YMM avx2
+cglobal interp_4tap_vert_%1_8x%2, 4, 7, 8
     mov             r4d, r4m
     shl             r4d, 6
 
@@ -5578,15 +5578,17 @@
     mova            m7, [pw_2000]
 %endif
     lea             r6, [r3 * 3]
-%rep 2
+%rep %2 / 16
     PROCESS_CHROMA_AVX2_W8_16R %1
     lea             r2, [r2 + r3 * 4]
 %endrep
     RET
 %endmacro
 
-    FILTER_VER_CHROMA_AVX2_8x32 pp
-    FILTER_VER_CHROMA_AVX2_8x32 ps
+    FILTER_VER_CHROMA_AVX2_8xN pp, 32
+    FILTER_VER_CHROMA_AVX2_8xN ps, 32
+    FILTER_VER_CHROMA_AVX2_8xN pp, 64
+    FILTER_VER_CHROMA_AVX2_8xN ps, 64
 
 %macro PROCESS_CHROMA_AVX2_W8_4R 0
     movq            xm1, [r0]                       ; m1 = row 0