[x265] [PATCH] asm-avx2: filter_vpp[4x8], filter_vps[4x8]: improve 414c->289c, 353c->250c

Divya Manivannan divya at multicorewareinc.com
Wed Feb 25 10:10:11 CET 2015


The above patch is for review only.

On Wed, Feb 25, 2015 at 2:25 PM, Divya Manivannan <
divya at multicorewareinc.com> wrote:

> # HG changeset patch
> # User Divya Manivannan <divya at multicorewareinc.com>
> # Date 1424854495 -19800
> #      Wed Feb 25 14:24:55 2015 +0530
> # Node ID 34b53460c45c69a5b9e318c094c1c8c7744b4e99
> # Parent  02bac78bde961d60d180e59b5260fad93b98d9b4
> asm-avx2: filter_vpp[4x8], filter_vps[4x8]: improve 414c->289c, 353c->250c
>
> diff -r 02bac78bde96 -r 34b53460c45c source/common/x86/asm-primitives.cpp
> --- a/source/common/x86/asm-primitives.cpp      Wed Feb 25 13:46:58 2015
> +0530
> +++ b/source/common/x86/asm-primitives.cpp      Wed Feb 25 14:24:55 2015
> +0530
> @@ -1799,9 +1799,12 @@
>          p.chroma[X265_CSP_I420].pu[CHROMA_420_4x4].filter_vpp =
> x265_interp_4tap_vert_pp_4x4_avx2;
>          p.chroma[X265_CSP_I420].pu[CHROMA_420_8x8].filter_vpp =
> x265_interp_4tap_vert_pp_8x8_avx2;
>          p.chroma[X265_CSP_I420].pu[CHROMA_420_2x4].filter_vpp =
> x265_interp_4tap_vert_pp_2x4_avx2;
> +        p.chroma[X265_CSP_I420].pu[CHROMA_420_4x8].filter_vpp =
> x265_interp_4tap_vert_pp_4x8_avx2;
>          p.chroma[X265_CSP_I420].pu[CHROMA_420_8x4].filter_vpp =
> x265_interp_4tap_vert_pp_8x4_avx2;
> +
>          p.chroma[X265_CSP_I420].pu[CHROMA_420_2x4].filter_vps =
> x265_interp_4tap_vert_ps_2x4_avx2;
>          p.chroma[X265_CSP_I420].pu[CHROMA_420_4x4].filter_vps =
> x265_interp_4tap_vert_ps_4x4_avx2;
> +        p.chroma[X265_CSP_I420].pu[CHROMA_420_4x8].filter_vps =
> x265_interp_4tap_vert_ps_4x8_avx2;
>          p.chroma[X265_CSP_I420].pu[CHROMA_420_8x4].filter_vps =
> x265_interp_4tap_vert_ps_8x4_avx2;
>          p.chroma[X265_CSP_I420].pu[CHROMA_420_8x8].filter_vps =
> x265_interp_4tap_vert_ps_8x8_avx2;
>          // color space i422
> diff -r 02bac78bde96 -r 34b53460c45c source/common/x86/ipfilter8.asm
> --- a/source/common/x86/ipfilter8.asm   Wed Feb 25 13:46:58 2015 +0530
> +++ b/source/common/x86/ipfilter8.asm   Wed Feb 25 14:24:55 2015 +0530
> @@ -2613,6 +2613,94 @@
>
>  FILTER_VER_CHROMA_AVX2_4x4 pp
>  FILTER_VER_CHROMA_AVX2_4x4 ps
> +
> +%macro FILTER_VER_CHROMA_AVX2_4x8 1
> +INIT_YMM avx2
> +cglobal interp_4tap_vert_%1_4x8, 4, 6, 5
> +    mov             r4d, r4m
> +    shl             r4d, 6
> +    sub             r0, r1
> +
> +%ifdef PIC
> +    lea             r5, [tab_ChromaCoeffVer_32]
> +    add             r5, r4
> +%else
> +    lea             r5, [tab_ChromaCoeffVer_32 + r4]
> +%endif
> +
> +    lea             r4, [r1 * 3]
> +
> +    movd            xm1, [r0]
> +    pinsrd          xm1, [r0 + r1], 1
> +    pinsrd          xm1, [r0 + r1 * 2], 2
> +    pinsrd          xm1, [r0 + r4], 3                       ; m1 = row[3
> 2 1 0]
> +    lea             r0, [r0 + r1 * 4]
> +    movd            xm2, [r0]
> +    pinsrd          xm2, [r0 + r1], 1
> +    pinsrd          xm2, [r0 + r1 * 2], 2
> +    pinsrd          xm2, [r0 + r4], 3                       ; m2 = row[7
> 6 5 4]
> +    vinserti128     m1, m1, xm2, 1                          ; m1 = row[7
> 6 5 4 3 2 1 0]
> +    lea             r0, [r0 + r1 * 4]
> +    movd            xm3, [r0]
> +    pinsrd          xm3, [r0 + r1], 1
> +    pinsrd          xm3, [r0 + r1 * 2], 2                   ; m3 = row[x
> 10 9 8]
> +    vinserti128     m2, m2, xm3, 1                          ; m2 = row[x
> 10 9 8 7 6 5 4]
> +    mova            m3, [interp4_vpp_shuf1]
> +    vpermd          m0, m3, m1                              ; m0 = row[4
> 3 3 2 2 1 1 0]
> +    vpermd          m4, m3, m2                              ; m4 = row[8
> 7 7 6 6 5 5 4]
> +    mova            m3, [interp4_vpp_shuf1 + mmsize]
> +    vpermd          m1, m3, m1                              ; m1 = row[6
> 5 5 4 4 3 3 2]
> +    vpermd          m2, m3, m2                              ; m2 = row[10
> 9 9 8 8 7 7 6]
> +
> +    mova            m3, [interp4_vpp_shuf]
> +    pshufb          m0, m0, m3
> +    pshufb          m1, m1, m3
> +    pshufb          m2, m2, m3
> +    pshufb          m4, m4, m3
> +    pmaddubsw       m0, [r5]
> +    pmaddubsw       m4, [r5]
> +    pmaddubsw       m1, [r5 + mmsize]
> +    pmaddubsw       m2, [r5 + mmsize]
> +    paddw           m0, m1                                  ; m0 = WORD
> ROW[3 2 1 0]
> +    paddw           m4, m2                                  ; m4 = WORD
> ROW[7 6 5 4]
> +%ifidn %1,pp
> +    pmulhrsw        m0, [pw_512]
> +    pmulhrsw        m4, [pw_512]
> +    packuswb        m0, m4
> +    vextracti128    xm1, m0, 1
> +    lea             r5, [r3 * 3]
> +    movd            [r2], xm0
> +    pextrd          [r2 + r3], xm0, 1
> +    movd            [r2 + r3 * 2], xm1
> +    pextrd          [r2 + r5], xm1, 1
> +    lea             r2, [r2 + r3 * 4]
> +    pextrd          [r2], xm0, 2
> +    pextrd          [r2 + r3], xm0, 3
> +    pextrd          [r2 + r3 * 2], xm1, 2
> +    pextrd          [r2 + r5], xm1, 3
> +%else
> +    add             r3d, r3d
> +    psubw           m0, [pw_2000]
> +    psubw           m4, [pw_2000]
> +    vextracti128    xm1, m0, 1
> +    vextracti128    xm2, m4, 1
> +    lea             r5, [r3 * 3]
> +    movq            [r2], xm0
> +    movhps          [r2 + r3], xm0
> +    movq            [r2 + r3 * 2], xm1
> +    movhps          [r2 + r5], xm1
> +    lea             r2, [r2 + r3 * 4]
> +    movq            [r2], xm4
> +    movhps          [r2 + r3], xm4
> +    movq            [r2 + r3 * 2], xm2
> +    movhps          [r2 + r5], xm2
> +%endif
> +    RET
> +%endmacro
> +
> +FILTER_VER_CHROMA_AVX2_4x8 pp
> +FILTER_VER_CHROMA_AVX2_4x8 ps
> +
>
>  ;-----------------------------------------------------------------------------
>  ; void interp_4tap_vert_pp_%1x%2(pixel *src, intptr_t srcStride, pixel
> *dst, intptr_t dstStride, int coeffIdx)
>
>  ;-----------------------------------------------------------------------------
>
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