[x265] [PATCH] asm: 10bpp avx2 code for intra_pred_ang32x32 mode 5 & 31
dnyaneshwar at multicorewareinc.com
dnyaneshwar at multicorewareinc.com
Wed Jun 10 10:36:25 CEST 2015
# HG changeset patch
# User Dnyaneshwar G <dnyaneshwar at multicorewareinc.com>
# Date 1433914676 -19800
# Wed Jun 10 11:07:56 2015 +0530
# Node ID 2188ac83f8f59c9e68bc90c540f3951b74f2a32a
# Parent 6245476add8f0562e3ccb657f572ff94fe96adf0
asm: 10bpp avx2 code for intra_pred_ang32x32 mode 5 & 31
performance improvement over SSE:
intra_ang_32x32[ 5] 8772c->4360c, 48%
intra_ang_32x32[31] 6308c->2923c, 53%
diff -r 6245476add8f -r 2188ac83f8f5 source/common/x86/asm-primitives.cpp
--- a/source/common/x86/asm-primitives.cpp Wed Jun 10 11:54:27 2015 +0530
+++ b/source/common/x86/asm-primitives.cpp Wed Jun 10 11:07:56 2015 +0530
@@ -1259,6 +1259,8 @@
p.cu[BLOCK_32x32].intra_pred[2] = x265_intra_pred_ang32_2_avx2;
p.cu[BLOCK_32x32].intra_pred[3] = x265_intra_pred_ang32_3_avx2;
p.cu[BLOCK_32x32].intra_pred[4] = x265_intra_pred_ang32_4_avx2;
+ p.cu[BLOCK_32x32].intra_pred[5] = x265_intra_pred_ang32_5_avx2;
+ p.cu[BLOCK_32x32].intra_pred[31] = x265_intra_pred_ang32_31_avx2;
p.cu[BLOCK_32x32].intra_pred[32] = x265_intra_pred_ang32_32_avx2;
p.cu[BLOCK_32x32].intra_pred[33] = x265_intra_pred_ang32_33_avx2;
p.cu[BLOCK_32x32].intra_pred[34] = x265_intra_pred_ang32_2_avx2;
diff -r 6245476add8f -r 2188ac83f8f5 source/common/x86/intrapred.h
--- a/source/common/x86/intrapred.h Wed Jun 10 11:54:27 2015 +0530
+++ b/source/common/x86/intrapred.h Wed Jun 10 11:07:56 2015 +0530
@@ -278,6 +278,7 @@
void x265_intra_pred_ang32_2_avx2(pixel* dst, intptr_t dstStride, const pixel* srcPix, int dirMode, int bFilter);
void x265_intra_pred_ang32_3_avx2(pixel* dst, intptr_t dstStride, const pixel* srcPix, int dirMode, int bFilter);
void x265_intra_pred_ang32_4_avx2(pixel* dst, intptr_t dstStride, const pixel* srcPix, int dirMode, int bFilter);
+void x265_intra_pred_ang32_5_avx2(pixel* dst, intptr_t dstStride, const pixel* srcPix, int dirMode, int bFilter);
void x265_intra_pred_ang32_26_avx2(pixel* dst, intptr_t dstStride, const pixel* srcPix, int dirMode, int bFilter);
void x265_intra_pred_ang32_27_avx2(pixel* dst, intptr_t dstStride, const pixel* srcPix, int dirMode, int bFilter);
void x265_intra_pred_ang32_28_avx2(pixel* dst, intptr_t dstStride, const pixel* srcPix, int dirMode, int bFilter);
diff -r 6245476add8f -r 2188ac83f8f5 source/common/x86/intrapred16.asm
--- a/source/common/x86/intrapred16.asm Wed Jun 10 11:54:27 2015 +0530
+++ b/source/common/x86/intrapred16.asm Wed Jun 10 11:07:56 2015 +0530
@@ -13561,6 +13561,215 @@
call ang32_mode_4_32
RET
+
+;; angle 32, modes 5 and 31
+cglobal ang32_mode_5_31
+ test r6d, r6d
+
+ movu m0, [r2 + 2] ; [16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1]
+ movu m1, [r2 + 4] ; [17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2]
+
+ punpcklwd m3, m0, m1 ; [13 12 12 11 11 10 10 9 5 4 4 3 3 2 2 1]
+ punpckhwd m0, m1 ; [17 16 16 15 15 14 14 13 9 8 8 7 7 6 6 5]
+
+ movu m1, [r2 + 18] ; [24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9]
+ movu m4, [r2 + 20] ; [25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10]
+ punpcklwd m2, m1, m4 ; [21 20 20 19 19 18 18 17 13 12 12 11 11 10 10 9]
+ punpckhwd m1, m4 ; [25 24 24 23 23 22 22 21 17 16 16 15 15 14 14 13]
+
+ pmaddwd m4, m3, [r3 - 15 * 32] ; [1]
+ paddd m4, [pd_16]
+ psrld m4, 5
+ pmaddwd m5, m0, [r3 - 15 * 32]
+ paddd m5, [pd_16]
+ psrld m5, 5
+ packusdw m4, m5
+
+ pmaddwd m5, m3, [r3 + 2 * 32] ; [18]
+ paddd m5, [pd_16]
+ psrld m5, 5
+ pmaddwd m8, m0, [r3 + 2 * 32]
+ paddd m8, [pd_16]
+ psrld m8, 5
+ packusdw m5, m8
+
+ palignr m7, m0, m3, 4
+ pmaddwd m6, m7, [r3 - 13 * 32] ; [3]
+ paddd m6, [pd_16]
+ psrld m6, 5
+ palignr m8, m2, m0, 4
+ pmaddwd m9, m8, [r3 - 13 * 32]
+ paddd m9, [pd_16]
+ psrld m9, 5
+ packusdw m6, m9
+
+ pmaddwd m7, [r3 + 4 * 32] ; [20]
+ paddd m7, [pd_16]
+ psrld m7, 5
+ pmaddwd m8, [r3 + 4 * 32]
+ paddd m8, [pd_16]
+ psrld m8, 5
+ packusdw m7, m8
+
+ palignr m9, m0, m3, 8
+ pmaddwd m8, m9, [r3 - 11 * 32] ; [5]
+ paddd m8, [pd_16]
+ psrld m8, 5
+ palignr m10, m2, m0, 8
+ pmaddwd m11, m10, [r3 - 11 * 32]
+ paddd m11, [pd_16]
+ psrld m11, 5
+ packusdw m8, m11
+
+ pmaddwd m9, [r3 + 6 * 32] ; [22]
+ paddd m9, [pd_16]
+ psrld m9, 5
+ pmaddwd m10, [r3 + 6 * 32]
+ paddd m10, [pd_16]
+ psrld m10, 5
+ packusdw m9, m10
+
+ palignr m11, m0, m3, 12
+ pmaddwd m10, m11, [r3 - 9 * 32] ; [7]
+ paddd m10, [pd_16]
+ psrld m10, 5
+ palignr m12, m2, m0, 12
+ pmaddwd m3, m12, [r3 - 9 * 32]
+ paddd m3, [pd_16]
+ psrld m3, 5
+ packusdw m10, m3
+
+ pmaddwd m11, [r3 + 8 * 32] ; [24]
+ paddd m11, [pd_16]
+ psrld m11, 5
+ pmaddwd m12, [r3 + 8 * 32]
+ paddd m12, [pd_16]
+ psrld m12, 5
+ packusdw m11, m12
+
+ TRANSPOSE_STORE_AVX2 4, 5, 6, 7, 8, 9, 10, 11, 12, 3, 0
+
+ pmaddwd m4, m0, [r3 - 7 * 32] ; [9]
+ paddd m4, [pd_16]
+ psrld m4, 5
+ pmaddwd m5, m2, [r3 - 7 * 32]
+ paddd m5, [pd_16]
+ psrld m5, 5
+ packusdw m4, m5
+
+ pmaddwd m5, m0, [r3 + 10 * 32] ; [26]
+ paddd m5, [pd_16]
+ psrld m5, 5
+ pmaddwd m3, m2, [r3 + 10 * 32]
+ paddd m3, [pd_16]
+ psrld m3, 5
+ packusdw m5, m3
+
+ palignr m7, m2, m0, 4
+ pmaddwd m6, m7, [r3 - 5 * 32] ; [11]
+ paddd m6, [pd_16]
+ psrld m6, 5
+ palignr m8, m1, m2, 4
+ pmaddwd m9, m8, [r3 - 5 * 32]
+ paddd m9, [pd_16]
+ psrld m9, 5
+ packusdw m6, m9
+
+ pmaddwd m7, [r3 + 12 * 32] ; [28]
+ paddd m7, [pd_16]
+ psrld m7, 5
+ pmaddwd m8, [r3 + 12 * 32]
+ paddd m8, [pd_16]
+ psrld m8, 5
+ packusdw m7, m8
+
+ palignr m9, m2, m0, 8
+ pmaddwd m8, m9, [r3 - 3 * 32] ; [13]
+ paddd m8, [pd_16]
+ psrld m8, 5
+ palignr m3, m1, m2, 8
+ pmaddwd m10, m3, [r3 - 3 * 32]
+ paddd m10, [pd_16]
+ psrld m10, 5
+ packusdw m8, m10
+
+ pmaddwd m9, [r3 + 14 * 32] ; [30]
+ paddd m9, [pd_16]
+ psrld m9, 5
+ pmaddwd m3, [r3 + 14 * 32]
+ paddd m3, [pd_16]
+ psrld m3, 5
+ packusdw m9, m3
+
+ palignr m10, m2, m0, 12
+ pmaddwd m10, [r3 - 1 * 32] ; [15]
+ paddd m10, [pd_16]
+ psrld m10, 5
+ palignr m11, m1, m2, 12
+ pmaddwd m11, [r3 - 1 * 32]
+ paddd m11, [pd_16]
+ psrld m11, 5
+ packusdw m10, m11
+
+ pmaddwd m2, [r3 - 16 * 32] ; [0]
+ paddd m2, [pd_16]
+ psrld m2, 5
+ pmaddwd m1, [r3 - 16 * 32]
+ paddd m1, [pd_16]
+ psrld m1, 5
+ packusdw m2, m1
+ TRANSPOSE_STORE_AVX2 4, 5, 6, 7, 8, 9, 10, 2, 0, 1, 16
+ ret
+
+cglobal intra_pred_ang32_5, 3,8,13
+ add r2, 128
+ xor r6d, r6d
+ lea r3, [ang_table_avx2 + 16 * 32]
+ add r1d, r1d
+ lea r4, [r1 * 3]
+ lea r7, [r0 + 8 * r1]
+
+ call ang16_mode_5_31
+
+ add r2, 18
+ lea r0, [r0 + 32]
+
+ call ang32_mode_5_31
+
+ add r2, 14
+ lea r0, [r7 + 8 * r1]
+
+ call ang16_mode_5_31
+
+ add r2, 18
+ lea r0, [r0 + 32]
+
+ call ang32_mode_5_31
+ RET
+
+cglobal intra_pred_ang32_31, 3,7,13
+ xor r6d, r6d
+ inc r6d
+ lea r3, [ang_table_avx2 + 16 * 32]
+ add r1d, r1d
+ lea r4, [r1 * 3]
+ lea r5, [r0 + 32]
+
+ call ang16_mode_5_31
+
+ add r2, 18
+
+ call ang32_mode_5_31
+
+ add r2, 14
+ mov r0, r5
+
+ call ang16_mode_5_31
+
+ add r2, 18
+
+ call ang32_mode_5_31
+ RET
;-------------------------------------------------------------------------------------------------------
; end of avx2 code for intra_pred_ang32 mode 2 to 34
;-------------------------------------------------------------------------------------------------------
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