[x265] [PATCH 5 of 7] asm-intra_pred_ang16_29: improved, 866.95c -> 493.20c over SSE4 asm code
praveen at multicorewareinc.com
praveen at multicorewareinc.com
Mon Mar 16 05:55:34 CET 2015
# HG changeset patch
# User Praveen Tiwari <praveen at multicorewareinc.com>
# Date 1426255819 -19800
# Node ID 3be8f0f4e90c232c2d475f0d4240bc5cf391716a
# Parent 986aec8f2698250888d4c639542c5f6500edc60d
asm-intra_pred_ang16_29: improved, 866.95c -> 493.20c over SSE4 asm code
AVX2:
intra_ang_16x16[29] 18.72x 493.20 9231.12
SSE4:
intra_ang_16x16[29] 10.46x 866.95 9072.53
diff -r 986aec8f2698 -r 3be8f0f4e90c source/common/x86/asm-primitives.cpp
--- a/source/common/x86/asm-primitives.cpp Fri Mar 13 18:17:38 2015 +0530
+++ b/source/common/x86/asm-primitives.cpp Fri Mar 13 19:40:19 2015 +0530
@@ -1509,6 +1509,7 @@
p.cu[BLOCK_16x16].intra_pred[25] = x265_intra_pred_ang16_25_avx2;
p.cu[BLOCK_16x16].intra_pred[28] = x265_intra_pred_ang16_28_avx2;
p.cu[BLOCK_16x16].intra_pred[27] = x265_intra_pred_ang16_27_avx2;
+ p.cu[BLOCK_16x16].intra_pred[29] = x265_intra_pred_ang16_29_avx2;
// copy_sp primitives
p.cu[BLOCK_16x16].copy_sp = x265_blockcopy_sp_16x16_avx2;
diff -r 986aec8f2698 -r 3be8f0f4e90c source/common/x86/intrapred.h
--- a/source/common/x86/intrapred.h Fri Mar 13 18:17:38 2015 +0530
+++ b/source/common/x86/intrapred.h Fri Mar 13 19:40:19 2015 +0530
@@ -186,6 +186,7 @@
void x265_intra_pred_ang16_25_avx2(pixel* dst, intptr_t dstStride, const pixel* srcPix, int dirMode, int bFilter);
void x265_intra_pred_ang16_28_avx2(pixel* dst, intptr_t dstStride, const pixel* srcPix, int dirMode, int bFilter);
void x265_intra_pred_ang16_27_avx2(pixel* dst, intptr_t dstStride, const pixel* srcPix, int dirMode, int bFilter);
+void x265_intra_pred_ang16_29_avx2(pixel* dst, intptr_t dstStride, const pixel* srcPix, int dirMode, int bFilter);
void x265_all_angs_pred_4x4_sse4(pixel *dest, pixel *refPix, pixel *filtPix, int bLuma);
void x265_all_angs_pred_8x8_sse4(pixel *dest, pixel *refPix, pixel *filtPix, int bLuma);
void x265_all_angs_pred_16x16_sse4(pixel *dest, pixel *refPix, pixel *filtPix, int bLuma);
diff -r 986aec8f2698 -r 3be8f0f4e90c source/common/x86/intrapred8.asm
--- a/source/common/x86/intrapred8.asm Fri Mar 13 18:17:38 2015 +0530
+++ b/source/common/x86/intrapred8.asm Fri Mar 13 19:40:19 2015 +0530
@@ -150,6 +150,18 @@
ALIGN 32
intra_pred_shuff_0_15: db 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15, 15
+
+ALIGN 32
+c_ang16_mode_29: db 23, 9, 23, 9, 23, 9, 23, 9, 23, 9, 23, 9, 23, 9, 23, 9, 14, 18, 14, 18, 14, 18, 14, 18, 14, 18, 14, 18, 14, 18, 14, 18
+ db 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27
+ db 28, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4, 19, 13, 19, 13, 19, 13, 19, 13, 19, 13, 19, 13, 19, 13, 19, 13
+ db 10, 22, 10, 22, 10, 22, 10, 22, 10, 22, 10, 22, 10, 22, 10, 22, 1, 31, 1, 31, 1, 31, 1, 31, 1, 31, 1, 31, 1, 31, 1, 31
+ db 24, 8, 24, 8, 24, 8, 24, 8, 24, 8, 24, 8, 24, 8, 24, 8, 15, 17, 15, 17, 15, 17, 15, 17, 15, 17, 15, 17, 15, 17, 15, 17
+ db 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26
+ db 29, 3, 29, 3, 29, 3, 29, 3, 29, 3, 29, 3, 29, 3, 29, 3, 20, 12, 20, 12, 20, 12, 20, 12, 20, 12, 20, 12, 20, 12, 20, 12
+ db 11, 21, 11, 21, 11, 21, 11, 21, 11, 21, 11, 21, 11, 21, 11, 21, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30
+ db 25, 7, 25, 7, 25, 7, 25, 7, 25, 7, 25, 7, 25, 7, 25, 7, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16
+
ALIGN 32
;; (blkSize - 1 - x)
pw_planar4_0: dw 3, 2, 1, 0, 3, 2, 1, 0
@@ -10831,3 +10843,68 @@
vextracti128 xm4, m3, 1
movu [r0 + r3], xm4
RET
+
+INIT_YMM avx2
+cglobal intra_pred_ang16_29, 3, 5, 5
+ mova m0, [pw_1024]
+ mova m5, [intra_pred_shuff_0_8]
+ lea r3, [3 * r1]
+ lea r4, [c_ang16_mode_29]
+
+ vbroadcasti128 m1, [r2 + 1]
+ pshufb m1, m5
+ vbroadcasti128 m2, [r2 + 9]
+ pshufb m2, m5
+
+ INTRA_PRED_ANG16_MC0 r0, r0 + r1, 0
+
+ vperm2i128 m1, m1, m2, 00100000b
+ pmaddubsw m3, m1, [r4 + 1 * mmsize]
+ pmulhrsw m3, m0
+ packuswb m3, m3
+ vpermq m3, m3, 11011000b
+ movu [r0 + 2 * r1], xm3
+
+ vbroadcasti128 m1, [r2 + 2]
+ pshufb m1, m5
+ vbroadcasti128 m2, [r2 + 10]
+ pshufb m2, m5
+
+ INTRA_PRED_ANG16_MC0 r0 + r3, r0 + 4 * r1, 2
+
+ lea r0, [r0 + r1 * 4]
+ INTRA_PRED_ANG16_MC0 r0 + r1, r0 + 2 * r1, 3
+
+ vbroadcasti128 m1, [r2 + 3]
+ pshufb m1, m5
+ vbroadcasti128 m2, [r2 + 11]
+ pshufb m2, m5
+
+ lea r4, [r4 + 4 * mmsize]
+ INTRA_PRED_ANG16_MC0 r0 + r3, r0 + 4 * r1, 0
+ lea r0, [r0 + r1 * 4]
+
+ vperm2i128 m1, m1, m2, 00100000b
+ pmaddubsw m3, m1, [r4 + 1 * mmsize]
+ pmulhrsw m3, m0
+ packuswb m3, m3
+ vpermq m3, m3, 11011000b
+ movu [r0 + r1], xm3
+
+ vbroadcasti128 m1, [r2 + 4]
+ pshufb m1, m5
+ vbroadcasti128 m2, [r2 + 12]
+ pshufb m2, m5
+
+ INTRA_PRED_ANG16_MC0 r0 + 2 * r1, r0 + r3, 2
+ lea r0, [r0 + r1 * 4]
+ INTRA_PRED_ANG16_MC0 r0, r0 + r1, 3
+
+ lea r4, [r4 + 4 * mmsize]
+ vbroadcasti128 m1, [r2 + 5]
+ pshufb m1, m5
+ vbroadcasti128 m2, [r2 + 13]
+ pshufb m2, m5
+
+ INTRA_PRED_ANG16_MC0 r0 + 2 * r1, r0 + r3, 0
+ RET
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