[x265] [PATCH 1 of 2] asm: filter_vsp[8x4], filter_vss[8x4] in avx2: 598c->293c, 586c->290c
Divya Manivannan
divya at multicorewareinc.com
Tue Mar 17 05:49:07 CET 2015
# HG changeset patch
# User Divya Manivannan <divya at multicorewareinc.com>
# Date 1426567251 -19800
# Tue Mar 17 10:10:51 2015 +0530
# Node ID 0e800a2489df77b3be509c202df3db805178b5fd
# Parent b9948752d5516a72eeaf824e3ee6f0feb097381c
asm: filter_vsp[8x4], filter_vss[8x4] in avx2: 598c->293c, 586c->290c
diff -r b9948752d551 -r 0e800a2489df source/common/x86/asm-primitives.cpp
--- a/source/common/x86/asm-primitives.cpp Mon Mar 16 20:40:12 2015 -0500
+++ b/source/common/x86/asm-primitives.cpp Tue Mar 17 10:10:51 2015 +0530
@@ -1674,6 +1674,7 @@
p.chroma[X265_CSP_I420].pu[CHROMA_420_4x2].filter_vsp = x265_interp_4tap_vert_sp_4x2_avx2;
p.chroma[X265_CSP_I420].pu[CHROMA_420_4x8].filter_vsp = x265_interp_4tap_vert_sp_4x8_avx2;
p.chroma[X265_CSP_I420].pu[CHROMA_420_4x16].filter_vsp = x265_interp_4tap_vert_sp_4x16_avx2;
+ p.chroma[X265_CSP_I420].pu[CHROMA_420_8x4].filter_vsp = x265_interp_4tap_vert_sp_8x4_avx2;
p.chroma[X265_CSP_I420].pu[CHROMA_420_16x32].filter_vsp = x265_interp_4tap_vert_sp_16x32_avx2;
p.chroma[X265_CSP_I420].pu[CHROMA_420_24x32].filter_vsp = x265_interp_4tap_vert_sp_24x32_avx2;
p.chroma[X265_CSP_I420].pu[CHROMA_420_32x16].filter_vsp = x265_interp_4tap_vert_sp_32x16_avx2;
@@ -1686,6 +1687,7 @@
p.chroma[X265_CSP_I420].pu[CHROMA_420_4x2].filter_vss = x265_interp_4tap_vert_ss_4x2_avx2;
p.chroma[X265_CSP_I420].pu[CHROMA_420_4x8].filter_vss = x265_interp_4tap_vert_ss_4x8_avx2;
p.chroma[X265_CSP_I420].pu[CHROMA_420_4x16].filter_vss = x265_interp_4tap_vert_ss_4x16_avx2;
+ p.chroma[X265_CSP_I420].pu[CHROMA_420_8x4].filter_vss = x265_interp_4tap_vert_ss_8x4_avx2;
p.chroma[X265_CSP_I420].pu[CHROMA_420_16x32].filter_vss = x265_interp_4tap_vert_ss_16x32_avx2;
p.chroma[X265_CSP_I420].pu[CHROMA_420_24x32].filter_vss = x265_interp_4tap_vert_ss_24x32_avx2;
p.chroma[X265_CSP_I420].pu[CHROMA_420_32x16].filter_vss = x265_interp_4tap_vert_ss_32x16_avx2;
diff -r b9948752d551 -r 0e800a2489df source/common/x86/ipfilter8.asm
--- a/source/common/x86/ipfilter8.asm Mon Mar 16 20:40:12 2015 -0500
+++ b/source/common/x86/ipfilter8.asm Tue Mar 17 10:10:51 2015 +0530
@@ -13773,6 +13773,116 @@
FILTER_VER_CHROMA_S_AVX2_NxN 24, 32, ss
FILTER_VER_CHROMA_S_AVX2_NxN 32, 32, ss
+%macro PROCESS_CHROMA_S_AVX2_W8_4R 1
+ movu xm0, [r0] ; m0 = row 0
+ movu xm1, [r0 + r1] ; m1 = row 1
+ punpckhwd xm2, xm0, xm1
+ punpcklwd xm0, xm1
+ vinserti128 m0, m0, xm2, 1
+ pmaddwd m0, [r5]
+ movu xm2, [r0 + r1 * 2] ; m2 = row 2
+ punpckhwd xm3, xm1, xm2
+ punpcklwd xm1, xm2
+ vinserti128 m1, m1, xm3, 1
+ pmaddwd m1, [r5]
+ movu xm3, [r0 + r4] ; m3 = row 3
+ punpckhwd xm4, xm2, xm3
+ punpcklwd xm2, xm3
+ vinserti128 m2, m2, xm4, 1
+ pmaddwd m4, m2, [r5 + 1 * mmsize]
+ paddd m0, m4
+ pmaddwd m2, [r5]
+ lea r0, [r0 + r1 * 4]
+ movu xm4, [r0] ; m4 = row 4
+ punpckhwd xm5, xm3, xm4
+ punpcklwd xm3, xm4
+ vinserti128 m3, m3, xm5, 1
+ pmaddwd m5, m3, [r5 + 1 * mmsize]
+ paddd m1, m5
+ pmaddwd m3, [r5]
+ movu xm5, [r0 + r1] ; m5 = row 5
+ punpckhwd xm6, xm4, xm5
+ punpcklwd xm4, xm5
+ vinserti128 m4, m4, xm6, 1
+ pmaddwd m4, [r5 + 1 * mmsize]
+ paddd m2, m4
+ movu xm6, [r0 + r1 * 2] ; m6 = row 6
+ punpckhwd xm4, xm5, xm6
+ punpcklwd xm5, xm6
+ vinserti128 m5, m5, xm4, 1
+ pmaddwd m5, [r5 + 1 * mmsize]
+ paddd m3, m5
+%ifidn %1,sp
+ paddd m0, m7
+ paddd m1, m7
+ paddd m2, m7
+ paddd m3, m7
+ psrad m0, 12
+ psrad m1, 12
+ psrad m2, 12
+ psrad m3, 12
+%else
+ psrad m0, 6
+ psrad m1, 6
+ psrad m2, 6
+ psrad m3, 6
+%endif
+ packssdw m0, m1
+ packssdw m2, m3
+%ifidn %1,sp
+ packuswb m0, m2
+ mova m3, [interp8_hps_shuf]
+ vpermd m0, m3, m0
+ vextracti128 xm2, m0, 1
+%else
+ vpermq m0, m0, 11011000b
+ vpermq m2, m2, 11011000b
+ vextracti128 xm1, m0, 1
+ vextracti128 xm3, m2, 1
+%endif
+%endmacro
+
+%macro FILTER_VER_CHROMA_S_AVX2_8x4 1
+INIT_YMM avx2
+cglobal interp_4tap_vert_%1_8x4, 4, 6, 8
+ mov r4d, r4m
+ shl r4d, 6
+ add r1d, r1d
+
+%ifdef PIC
+ lea r5, [pw_ChromaCoeffV]
+ add r5, r4
+%else
+ lea r5, [pw_ChromaCoeffV + r4]
+%endif
+
+ lea r4, [r1 * 3]
+ sub r0, r1
+%ifidn %1,sp
+ mova m7, [pd_526336]
+%else
+ add r3d, r3d
+%endif
+
+ PROCESS_CHROMA_S_AVX2_W8_4R %1
+ lea r4, [r3 * 3]
+%ifidn %1,sp
+ movq [r2], xm0
+ movhps [r2 + r3], xm0
+ movq [r2 + r3 * 2], xm2
+ movhps [r2 + r4], xm2
+%else
+ movu [r2], xm0
+ movu [r2 + r3], xm1
+ movu [r2 + r3 * 2], xm2
+ movu [r2 + r4], xm3
+%endif
+ RET
+%endmacro
+
+FILTER_VER_CHROMA_S_AVX2_8x4 sp
+FILTER_VER_CHROMA_S_AVX2_8x4 ss
+
;---------------------------------------------------------------------------------------------------------------------
; void interp_4tap_vertical_ss_%1x%2(int16_t *src, intptr_t srcStride, int16_t *dst, intptr_t dstStride, int coeffIdx)
;---------------------------------------------------------------------------------------------------------------------
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