[x265] [PATCH 2 of 2] asm: filter_vsp[12x16], filter_vss[12x16] in avx2: 3987c->1530c, 3305c->1482c
Divya Manivannan
divya at multicorewareinc.com
Tue Mar 17 05:49:08 CET 2015
# HG changeset patch
# User Divya Manivannan <divya at multicorewareinc.com>
# Date 1426567659 -19800
# Tue Mar 17 10:17:39 2015 +0530
# Node ID fded3766342a887f2074a701223b0a13806912b7
# Parent 0e800a2489df77b3be509c202df3db805178b5fd
asm: filter_vsp[12x16], filter_vss[12x16] in avx2: 3987c->1530c, 3305c->1482c
diff -r 0e800a2489df -r fded3766342a source/common/x86/asm-primitives.cpp
--- a/source/common/x86/asm-primitives.cpp Tue Mar 17 10:10:51 2015 +0530
+++ b/source/common/x86/asm-primitives.cpp Tue Mar 17 10:17:39 2015 +0530
@@ -1675,6 +1675,7 @@
p.chroma[X265_CSP_I420].pu[CHROMA_420_4x8].filter_vsp = x265_interp_4tap_vert_sp_4x8_avx2;
p.chroma[X265_CSP_I420].pu[CHROMA_420_4x16].filter_vsp = x265_interp_4tap_vert_sp_4x16_avx2;
p.chroma[X265_CSP_I420].pu[CHROMA_420_8x4].filter_vsp = x265_interp_4tap_vert_sp_8x4_avx2;
+ p.chroma[X265_CSP_I420].pu[CHROMA_420_12x16].filter_vsp = x265_interp_4tap_vert_sp_12x16_avx2;
p.chroma[X265_CSP_I420].pu[CHROMA_420_16x32].filter_vsp = x265_interp_4tap_vert_sp_16x32_avx2;
p.chroma[X265_CSP_I420].pu[CHROMA_420_24x32].filter_vsp = x265_interp_4tap_vert_sp_24x32_avx2;
p.chroma[X265_CSP_I420].pu[CHROMA_420_32x16].filter_vsp = x265_interp_4tap_vert_sp_32x16_avx2;
@@ -1688,6 +1689,7 @@
p.chroma[X265_CSP_I420].pu[CHROMA_420_4x8].filter_vss = x265_interp_4tap_vert_ss_4x8_avx2;
p.chroma[X265_CSP_I420].pu[CHROMA_420_4x16].filter_vss = x265_interp_4tap_vert_ss_4x16_avx2;
p.chroma[X265_CSP_I420].pu[CHROMA_420_8x4].filter_vss = x265_interp_4tap_vert_ss_8x4_avx2;
+ p.chroma[X265_CSP_I420].pu[CHROMA_420_12x16].filter_vss = x265_interp_4tap_vert_ss_12x16_avx2;
p.chroma[X265_CSP_I420].pu[CHROMA_420_16x32].filter_vss = x265_interp_4tap_vert_ss_16x32_avx2;
p.chroma[X265_CSP_I420].pu[CHROMA_420_24x32].filter_vss = x265_interp_4tap_vert_ss_24x32_avx2;
p.chroma[X265_CSP_I420].pu[CHROMA_420_32x16].filter_vss = x265_interp_4tap_vert_ss_32x16_avx2;
diff -r 0e800a2489df -r fded3766342a source/common/x86/ipfilter8.asm
--- a/source/common/x86/ipfilter8.asm Tue Mar 17 10:10:51 2015 +0530
+++ b/source/common/x86/ipfilter8.asm Tue Mar 17 10:17:39 2015 +0530
@@ -13883,6 +13883,45 @@
FILTER_VER_CHROMA_S_AVX2_8x4 sp
FILTER_VER_CHROMA_S_AVX2_8x4 ss
+%macro FILTER_VER_CHROMA_S_AVX2_12x16 1
+INIT_YMM avx2
+%if ARCH_X86_64 == 1
+cglobal interp_4tap_vert_%1_12x16, 4, 9, 10
+ mov r4d, r4m
+ shl r4d, 6
+ add r1d, r1d
+
+%ifdef PIC
+ lea r5, [pw_ChromaCoeffV]
+ add r5, r4
+%else
+ lea r5, [pw_ChromaCoeffV + r4]
+%endif
+
+ lea r4, [r1 * 3]
+ sub r0, r1
+%ifidn %1,sp
+ mova m9, [pd_526336]
+%else
+ add r3d, r3d
+%endif
+ lea r6, [r3 * 3]
+ PROCESS_CHROMA_S_AVX2_W8_16R %1
+%ifidn %1,sp
+ add r2, 8
+%else
+ add r2, 16
+%endif
+ add r0, 16
+ mova m7, m9
+ PROCESS_CHROMA_AVX2_W4_16R %1
+ RET
+%endif
+%endmacro
+
+FILTER_VER_CHROMA_S_AVX2_12x16 sp
+FILTER_VER_CHROMA_S_AVX2_12x16 ss
+
;---------------------------------------------------------------------------------------------------------------------
; void interp_4tap_vertical_ss_%1x%2(int16_t *src, intptr_t srcStride, int16_t *dst, intptr_t dstStride, int coeffIdx)
;---------------------------------------------------------------------------------------------------------------------
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