[x265] [PATCH 4 of 5] asm: filter_vsp[6x8], filter_vss[6x8] in avx2: 863c->653c, 823c->524c
Divya Manivannan
divya at multicorewareinc.com
Thu Mar 19 06:13:56 CET 2015
# HG changeset patch
# User Divya Manivannan <divya at multicorewareinc.com>
# Date 1426740297 -19800
# Thu Mar 19 10:14:57 2015 +0530
# Node ID ad53f152fce599c1801304a0fd1ed0c5992f834f
# Parent db0cad2b0212b7876a62090f95390427e5cc5dcd
asm: filter_vsp[6x8], filter_vss[6x8] in avx2: 863c->653c, 823c->524c
diff -r db0cad2b0212 -r ad53f152fce5 source/common/x86/asm-primitives.cpp
--- a/source/common/x86/asm-primitives.cpp Thu Mar 19 10:09:10 2015 +0530
+++ b/source/common/x86/asm-primitives.cpp Thu Mar 19 10:14:57 2015 +0530
@@ -1695,6 +1695,7 @@
p.chroma[X265_CSP_I420].pu[CHROMA_420_4x2].filter_vsp = x265_interp_4tap_vert_sp_4x2_avx2;
p.chroma[X265_CSP_I420].pu[CHROMA_420_4x8].filter_vsp = x265_interp_4tap_vert_sp_4x8_avx2;
p.chroma[X265_CSP_I420].pu[CHROMA_420_4x16].filter_vsp = x265_interp_4tap_vert_sp_4x16_avx2;
+ p.chroma[X265_CSP_I420].pu[CHROMA_420_6x8].filter_vsp = x265_interp_4tap_vert_sp_6x8_avx2;
p.chroma[X265_CSP_I420].pu[CHROMA_420_8x2].filter_vsp = x265_interp_4tap_vert_sp_8x2_avx2;
p.chroma[X265_CSP_I420].pu[CHROMA_420_8x4].filter_vsp = x265_interp_4tap_vert_sp_8x4_avx2;
p.chroma[X265_CSP_I420].pu[CHROMA_420_8x6].filter_vsp = x265_interp_4tap_vert_sp_8x6_avx2;
@@ -1719,6 +1720,7 @@
p.chroma[X265_CSP_I420].pu[CHROMA_420_4x2].filter_vss = x265_interp_4tap_vert_ss_4x2_avx2;
p.chroma[X265_CSP_I420].pu[CHROMA_420_4x8].filter_vss = x265_interp_4tap_vert_ss_4x8_avx2;
p.chroma[X265_CSP_I420].pu[CHROMA_420_4x16].filter_vss = x265_interp_4tap_vert_ss_4x16_avx2;
+ p.chroma[X265_CSP_I420].pu[CHROMA_420_6x8].filter_vss = x265_interp_4tap_vert_ss_6x8_avx2;
p.chroma[X265_CSP_I420].pu[CHROMA_420_8x2].filter_vss = x265_interp_4tap_vert_ss_8x2_avx2;
p.chroma[X265_CSP_I420].pu[CHROMA_420_8x4].filter_vss = x265_interp_4tap_vert_ss_8x4_avx2;
p.chroma[X265_CSP_I420].pu[CHROMA_420_8x6].filter_vss = x265_interp_4tap_vert_ss_8x6_avx2;
diff -r db0cad2b0212 -r ad53f152fce5 source/common/x86/ipfilter8.asm
--- a/source/common/x86/ipfilter8.asm Thu Mar 19 10:09:10 2015 +0530
+++ b/source/common/x86/ipfilter8.asm Thu Mar 19 10:14:57 2015 +0530
@@ -15427,6 +15427,194 @@
FILTER_VER_CHROMA_S_AVX2_2x8 sp
FILTER_VER_CHROMA_S_AVX2_2x8 ss
+%macro FILTER_VER_CHROMA_S_AVX2_6x8 1
+INIT_YMM avx2
+cglobal interp_4tap_vert_%1_6x8, 4, 6, 8
+ mov r4d, r4m
+ shl r4d, 6
+ add r1d, r1d
+
+%ifdef PIC
+ lea r5, [pw_ChromaCoeffV]
+ add r5, r4
+%else
+ lea r5, [pw_ChromaCoeffV + r4]
+%endif
+
+ lea r4, [r1 * 3]
+ sub r0, r1
+%ifidn %1,sp
+ mova m7, [pd_526336]
+%else
+ add r3d, r3d
+%endif
+
+ movu xm0, [r0] ; m0 = row 0
+ movu xm1, [r0 + r1] ; m1 = row 1
+ punpckhwd xm2, xm0, xm1
+ punpcklwd xm0, xm1
+ vinserti128 m0, m0, xm2, 1
+ pmaddwd m0, [r5]
+ movu xm2, [r0 + r1 * 2] ; m2 = row 2
+ punpckhwd xm3, xm1, xm2
+ punpcklwd xm1, xm2
+ vinserti128 m1, m1, xm3, 1
+ pmaddwd m1, [r5]
+ movu xm3, [r0 + r4] ; m3 = row 3
+ punpckhwd xm4, xm2, xm3
+ punpcklwd xm2, xm3
+ vinserti128 m2, m2, xm4, 1
+ pmaddwd m4, m2, [r5 + 1 * mmsize]
+ pmaddwd m2, [r5]
+ paddd m0, m4
+ lea r0, [r0 + r1 * 4]
+ movu xm4, [r0] ; m4 = row 4
+ punpckhwd xm5, xm3, xm4
+ punpcklwd xm3, xm4
+ vinserti128 m3, m3, xm5, 1
+ pmaddwd m5, m3, [r5 + 1 * mmsize]
+ pmaddwd m3, [r5]
+ paddd m1, m5
+%ifidn %1,sp
+ paddd m0, m7
+ paddd m1, m7
+ psrad m0, 12
+ psrad m1, 12
+%else
+ psrad m0, 6
+ psrad m1, 6
+%endif
+ packssdw m0, m1
+
+ movu xm5, [r0 + r1] ; m5 = row 5
+ punpckhwd xm6, xm4, xm5
+ punpcklwd xm4, xm5
+ vinserti128 m4, m4, xm6, 1
+ pmaddwd m6, m4, [r5 + 1 * mmsize]
+ paddd m2, m6
+ pmaddwd m4, [r5]
+ movu xm6, [r0 + r1 * 2] ; m6 = row 6
+ punpckhwd xm1, xm5, xm6
+ punpcklwd xm5, xm6
+ vinserti128 m5, m5, xm1, 1
+ pmaddwd m1, m5, [r5 + 1 * mmsize]
+ pmaddwd m5, [r5]
+ paddd m3, m1
+%ifidn %1,sp
+ paddd m2, m7
+ paddd m3, m7
+ psrad m2, 12
+ psrad m3, 12
+%else
+ psrad m2, 6
+ psrad m3, 6
+%endif
+ packssdw m2, m3
+
+ movu xm1, [r0 + r4] ; m1 = row 7
+ punpckhwd xm3, xm6, xm1
+ punpcklwd xm6, xm1
+ vinserti128 m6, m6, xm3, 1
+ pmaddwd m3, m6, [r5 + 1 * mmsize]
+ pmaddwd m6, [r5]
+ paddd m4, m3
+
+ lea r4, [r3 * 3]
+%ifidn %1,sp
+ packuswb m0, m2
+ vextracti128 xm2, m0, 1
+ movd [r2], xm0
+ pextrw [r2 + 4], xm2, 0
+ pextrd [r2 + r3], xm0, 1
+ pextrw [r2 + r3 + 4], xm2, 2
+ pextrd [r2 + r3 * 2], xm0, 2
+ pextrw [r2 + r3 * 2 + 4], xm2, 4
+ pextrd [r2 + r4], xm0, 3
+ pextrw [r2 + r4 + 4], xm2, 6
+%else
+ movq [r2], xm0
+ movhps [r2 + r3], xm0
+ movq [r2 + r3 * 2], xm2
+ movhps [r2 + r4], xm2
+ vextracti128 xm0, m0, 1
+ vextracti128 xm3, m2, 1
+ movd [r2 + 8], xm0
+ pextrd [r2 + r3 + 8], xm0, 2
+ movd [r2 + r3 * 2 + 8], xm3
+ pextrd [r2 + r4 + 8], xm3, 2
+%endif
+ lea r2, [r2 + r3 * 4]
+ lea r0, [r0 + r1 * 4]
+ movu xm0, [r0] ; m0 = row 8
+ punpckhwd xm2, xm1, xm0
+ punpcklwd xm1, xm0
+ vinserti128 m1, m1, xm2, 1
+ pmaddwd m2, m1, [r5 + 1 * mmsize]
+ pmaddwd m1, [r5]
+ paddd m5, m2
+%ifidn %1,sp
+ paddd m4, m7
+ paddd m5, m7
+ psrad m4, 12
+ psrad m5, 12
+%else
+ psrad m4, 6
+ psrad m5, 6
+%endif
+ packssdw m4, m5
+
+ movu xm2, [r0 + r1] ; m2 = row 9
+ punpckhwd xm5, xm0, xm2
+ punpcklwd xm0, xm2
+ vinserti128 m0, m0, xm5, 1
+ pmaddwd m0, [r5 + 1 * mmsize]
+ paddd m6, m0
+ movu xm5, [r0 + r1 * 2] ; m5 = row 10
+ punpckhwd xm0, xm2, xm5
+ punpcklwd xm2, xm5
+ vinserti128 m2, m2, xm0, 1
+ pmaddwd m2, [r5 + 1 * mmsize]
+ paddd m1, m2
+
+%ifidn %1,sp
+ paddd m6, m7
+ paddd m1, m7
+ psrad m6, 12
+ psrad m1, 12
+%else
+ psrad m6, 6
+ psrad m1, 6
+%endif
+ packssdw m6, m1
+%ifidn %1,sp
+ packuswb m4, m6
+ vextracti128 xm6, m4, 1
+ movd [r2], xm4
+ pextrw [r2 + 4], xm6, 0
+ pextrd [r2 + r3], xm4, 1
+ pextrw [r2 + r3 + 4], xm6, 2
+ pextrd [r2 + r3 * 2], xm4, 2
+ pextrw [r2 + r3 * 2 + 4], xm6, 4
+ pextrd [r2 + r4], xm4, 3
+ pextrw [r2 + r4 + 4], xm6, 6
+%else
+ movq [r2], xm4
+ movhps [r2 + r3], xm4
+ movq [r2 + r3 * 2], xm6
+ movhps [r2 + r4], xm6
+ vextracti128 xm5, m4, 1
+ vextracti128 xm1, m6, 1
+ movd [r2 + 8], xm5
+ pextrd [r2 + r3 + 8], xm5, 2
+ movd [r2 + r3 * 2 + 8], xm1
+ pextrd [r2 + r4 + 8], xm1, 2
+%endif
+ RET
+%endmacro
+
+FILTER_VER_CHROMA_S_AVX2_6x8 sp
+FILTER_VER_CHROMA_S_AVX2_6x8 ss
+
;---------------------------------------------------------------------------------------------------------------------
; void interp_4tap_vertical_ss_%1x%2(int16_t *src, intptr_t srcStride, int16_t *dst, intptr_t dstStride, int coeffIdx)
;---------------------------------------------------------------------------------------------------------------------
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