[x265] [PATCH 3 of 5] asm: filter_vsp[2x8], filter_vss[2x8] in avx2: 482c->346c, 431c->306c
Divya Manivannan
divya at multicorewareinc.com
Thu Mar 19 06:13:55 CET 2015
# HG changeset patch
# User Divya Manivannan <divya at multicorewareinc.com>
# Date 1426739950 -19800
# Thu Mar 19 10:09:10 2015 +0530
# Node ID db0cad2b0212b7876a62090f95390427e5cc5dcd
# Parent 089e949f5e06849eb2126eb90f14a32de8706c9a
asm: filter_vsp[2x8], filter_vss[2x8] in avx2: 482c->346c, 431c->306c
diff -r 089e949f5e06 -r db0cad2b0212 source/common/x86/asm-primitives.cpp
--- a/source/common/x86/asm-primitives.cpp Thu Mar 19 10:04:06 2015 +0530
+++ b/source/common/x86/asm-primitives.cpp Thu Mar 19 10:09:10 2015 +0530
@@ -1691,6 +1691,7 @@
p.chroma[X265_CSP_I420].pu[CHROMA_420_16x16].filter_vsp = x265_interp_4tap_vert_sp_16x16_avx2;
p.chroma[X265_CSP_I420].pu[CHROMA_420_32x32].filter_vsp = x265_interp_4tap_vert_sp_32x32_avx2;
p.chroma[X265_CSP_I420].pu[CHROMA_420_2x4].filter_vsp = x265_interp_4tap_vert_sp_2x4_avx2;
+ p.chroma[X265_CSP_I420].pu[CHROMA_420_2x8].filter_vsp = x265_interp_4tap_vert_sp_2x8_avx2;
p.chroma[X265_CSP_I420].pu[CHROMA_420_4x2].filter_vsp = x265_interp_4tap_vert_sp_4x2_avx2;
p.chroma[X265_CSP_I420].pu[CHROMA_420_4x8].filter_vsp = x265_interp_4tap_vert_sp_4x8_avx2;
p.chroma[X265_CSP_I420].pu[CHROMA_420_4x16].filter_vsp = x265_interp_4tap_vert_sp_4x16_avx2;
@@ -1714,6 +1715,7 @@
p.chroma[X265_CSP_I420].pu[CHROMA_420_16x16].filter_vss = x265_interp_4tap_vert_ss_16x16_avx2;
p.chroma[X265_CSP_I420].pu[CHROMA_420_32x32].filter_vss = x265_interp_4tap_vert_ss_32x32_avx2;
p.chroma[X265_CSP_I420].pu[CHROMA_420_2x4].filter_vss = x265_interp_4tap_vert_ss_2x4_avx2;
+ p.chroma[X265_CSP_I420].pu[CHROMA_420_2x8].filter_vss = x265_interp_4tap_vert_ss_2x8_avx2;
p.chroma[X265_CSP_I420].pu[CHROMA_420_4x2].filter_vss = x265_interp_4tap_vert_ss_4x2_avx2;
p.chroma[X265_CSP_I420].pu[CHROMA_420_4x8].filter_vss = x265_interp_4tap_vert_ss_4x8_avx2;
p.chroma[X265_CSP_I420].pu[CHROMA_420_4x16].filter_vss = x265_interp_4tap_vert_ss_4x16_avx2;
diff -r 089e949f5e06 -r db0cad2b0212 source/common/x86/ipfilter8.asm
--- a/source/common/x86/ipfilter8.asm Thu Mar 19 10:04:06 2015 +0530
+++ b/source/common/x86/ipfilter8.asm Thu Mar 19 10:09:10 2015 +0530
@@ -15328,6 +15328,105 @@
FILTER_VER_CHROMA_S_AVX2_32x24 sp
FILTER_VER_CHROMA_S_AVX2_32x24 ss
+%macro FILTER_VER_CHROMA_S_AVX2_2x8 1
+INIT_YMM avx2
+cglobal interp_4tap_vert_%1_2x8, 4, 6, 7
+ mov r4d, r4m
+ shl r4d, 6
+ add r1d, r1d
+ sub r0, r1
+
+%ifdef PIC
+ lea r5, [pw_ChromaCoeffV]
+ add r5, r4
+%else
+ lea r5, [pw_ChromaCoeffV + r4]
+%endif
+
+ lea r4, [r1 * 3]
+%ifidn %1,sp
+ mova m6, [pd_526336]
+%else
+ add r3d, r3d
+%endif
+ movd xm0, [r0]
+ movd xm1, [r0 + r1]
+ punpcklwd xm0, xm1
+ movd xm2, [r0 + r1 * 2]
+ punpcklwd xm1, xm2
+ punpcklqdq xm0, xm1 ; m0 = [2 1 1 0]
+ movd xm3, [r0 + r4]
+ punpcklwd xm2, xm3
+ lea r0, [r0 + 4 * r1]
+ movd xm4, [r0]
+ punpcklwd xm3, xm4
+ punpcklqdq xm2, xm3 ; m2 = [4 3 3 2]
+ vinserti128 m0, m0, xm2, 1 ; m0 = [4 3 3 2 2 1 1 0]
+ movd xm1, [r0 + r1]
+ punpcklwd xm4, xm1
+ movd xm3, [r0 + r1 * 2]
+ punpcklwd xm1, xm3
+ punpcklqdq xm4, xm1 ; m4 = [6 5 5 4]
+ vinserti128 m2, m2, xm4, 1 ; m2 = [6 5 5 4 4 3 3 2]
+ pmaddwd m0, [r5]
+ pmaddwd m2, [r5 + 1 * mmsize]
+ paddd m0, m2
+ movd xm1, [r0 + r4]
+ punpcklwd xm3, xm1
+ lea r0, [r0 + 4 * r1]
+ movd xm2, [r0]
+ punpcklwd xm1, xm2
+ punpcklqdq xm3, xm1 ; m3 = [8 7 7 6]
+ vinserti128 m4, m4, xm3, 1 ; m4 = [8 7 7 6 6 5 5 4]
+ movd xm1, [r0 + r1]
+ punpcklwd xm2, xm1
+ movd xm5, [r0 + r1 * 2]
+ punpcklwd xm1, xm5
+ punpcklqdq xm2, xm1 ; m2 = [10 9 9 8]
+ vinserti128 m3, m3, xm2, 1 ; m3 = [10 9 9 8 8 7 7 6]
+ pmaddwd m4, [r5]
+ pmaddwd m3, [r5 + 1 * mmsize]
+ paddd m4, m3
+%ifidn %1,sp
+ paddd m0, m6
+ paddd m4, m6
+ psrad m0, 12
+ psrad m4, 12
+%else
+ psrad m0, 6
+ psrad m4, 6
+%endif
+ packssdw m0, m4
+ vextracti128 xm4, m0, 1
+ lea r4, [r3 * 3]
+%ifidn %1,sp
+ packuswb xm0, xm4
+ pextrw [r2], xm0, 0
+ pextrw [r2 + r3], xm0, 1
+ pextrw [r2 + 2 * r3], xm0, 4
+ pextrw [r2 + r4], xm0, 5
+ lea r2, [r2 + r3 * 4]
+ pextrw [r2], xm0, 2
+ pextrw [r2 + r3], xm0, 3
+ pextrw [r2 + 2 * r3], xm0, 6
+ pextrw [r2 + r4], xm0, 7
+%else
+ movd [r2], xm0
+ pextrd [r2 + r3], xm0, 1
+ movd [r2 + 2 * r3], xm4
+ pextrd [r2 + r4], xm4, 1
+ lea r2, [r2 + r3 * 4]
+ pextrd [r2], xm0, 2
+ pextrd [r2 + r3], xm0, 3
+ pextrd [r2 + 2 * r3], xm4, 2
+ pextrd [r2 + r4], xm4, 3
+%endif
+ RET
+%endmacro
+
+FILTER_VER_CHROMA_S_AVX2_2x8 sp
+FILTER_VER_CHROMA_S_AVX2_2x8 ss
+
;---------------------------------------------------------------------------------------------------------------------
; void interp_4tap_vertical_ss_%1x%2(int16_t *src, intptr_t srcStride, int16_t *dst, intptr_t dstStride, int coeffIdx)
;---------------------------------------------------------------------------------------------------------------------
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