[x265] [PATCH 4 of 5] asm: interp_4tap_vert_pp sse2
dtyx265 at gmail.com
dtyx265 at gmail.com
Fri May 8 22:57:15 CEST 2015
# HG changeset patch
# User David T Yuen <dtyx265 at gmail.com>
# Date 1431117805 25200
# Node ID 6dc172cd4d9d6625d0b2d6d114616c1ee664c83b
# Parent 9ca14d0867a3d9d10e8d74d9a4ec1431f937a1fd
asm: interp_4tap_vert_pp sse2
This replaces c code for 6x8 and 6x16 for 64-bit only
64-bit
./test/TestBench --testbench interp | grep vpp | grep " 6x"
chroma_vpp[ 6x8] 2.95x 2152.49 6340.15
chroma_vpp[ 6x16] 3.01x 4159.98 12530.22
diff -r 9ca14d0867a3 -r 6dc172cd4d9d source/common/x86/asm-primitives.cpp
--- a/source/common/x86/asm-primitives.cpp Fri May 08 13:34:34 2015 -0700
+++ b/source/common/x86/asm-primitives.cpp Fri May 08 13:43:25 2015 -0700
@@ -1384,6 +1384,10 @@
p.chroma[X265_CSP_I444].pu[LUMA_4x4].filter_vpp = x265_interp_4tap_vert_pp_4x4_sse2;
p.chroma[X265_CSP_I444].pu[LUMA_4x8].filter_vpp = x265_interp_4tap_vert_pp_4x8_sse2;
p.chroma[X265_CSP_I444].pu[LUMA_4x16].filter_vpp = x265_interp_4tap_vert_pp_4x16_sse2;
+#if X86_64
+ p.chroma[X265_CSP_I420].pu[CHROMA_420_6x8].filter_vpp = x265_interp_4tap_vert_pp_6x8_sse2;
+ p.chroma[X265_CSP_I422].pu[CHROMA_422_6x16].filter_vpp = x265_interp_4tap_vert_pp_6x16_sse2;
+#endif
ALL_LUMA_PU(luma_hpp, interp_8tap_horiz_pp, sse2);
p.pu[LUMA_4x4].luma_hpp = x265_interp_8tap_horiz_pp_4x4_sse2;
diff -r 9ca14d0867a3 -r 6dc172cd4d9d source/common/x86/ipfilter8.asm
--- a/source/common/x86/ipfilter8.asm Fri May 08 13:34:34 2015 -0700
+++ b/source/common/x86/ipfilter8.asm Fri May 08 13:43:25 2015 -0700
@@ -1372,6 +1372,161 @@
FILTER_V4_W4_H4_sse2 32
;-----------------------------------------------------------------------------
+;void interp_4tap_vert_pp_6x8(pixel *src, intptr_t srcStride, pixel *dst, intptr_t dstStride, int coeffIdx)
+;-----------------------------------------------------------------------------
+%macro FILTER_V4_W6_H4_sse2 1
+INIT_XMM sse2
+cglobal interp_4tap_vert_pp_6x%1, 4, 7, 10
+
+ mov r4d, r4m
+ sub r0, r1
+ shl r4d, 5
+ pxor m9, m9
+
+%ifdef PIC
+ lea r5, [tab_ChromaCoeffV]
+ mova m6, [r5 + r4]
+ mova m5, [r5 + r4 + 16]
+%else
+ mova m6, [tab_ChromaCoeffV + r4]
+ mova m5, [tab_ChromaCoeffV + r4 + 16]
+%endif
+
+ mova m4, [pw_32]
+ lea r5, [3 * r1]
+
+%assign x 1
+%rep %1/4
+ movq m0, [r0]
+ movq m1, [r0 + r1]
+ movq m2, [r0 + 2 * r1]
+ movq m3, [r0 + r5]
+
+ punpcklbw m0, m1
+ punpcklbw m1, m2
+ punpcklbw m2, m3
+
+ movhlps m7, m0
+ punpcklbw m0, m9
+ punpcklbw m7, m9
+ pmaddwd m0, m6
+ pmaddwd m7, m6
+ packssdw m0, m7
+
+ movhlps m8, m2
+ movq m7, m2
+ punpcklbw m8, m9
+ punpcklbw m7, m9
+ pmaddwd m8, m5
+ pmaddwd m7, m5
+ packssdw m7, m8
+
+ paddw m0, m7
+
+ paddw m0, m4
+ psraw m0, 6
+ packuswb m0, m0
+ movd [r2], m0
+ pextrw r6d, m0, 2
+ mov [r2 + 4], r6w
+
+ lea r0, [r0 + 4 * r1]
+
+ movq m0, [r0]
+ punpcklbw m3, m0
+
+ movhlps m8, m1
+ punpcklbw m1, m9
+ punpcklbw m8, m9
+ pmaddwd m1, m6
+ pmaddwd m8, m6
+ packssdw m1, m8
+
+ movhlps m8, m3
+ movq m7, m3
+ punpcklbw m8, m9
+ punpcklbw m7, m9
+ pmaddwd m8, m5
+ pmaddwd m7, m5
+ packssdw m7, m8
+
+ paddw m1, m7
+
+ paddw m1, m4
+ psraw m1, 6
+ packuswb m1, m1
+ movd [r2 + r3], m1
+ pextrw r6d, m1, 2
+ mov [r2 + r3 + 4], r6w
+ movq m1, [r0 + r1]
+ punpcklbw m7, m0, m1
+
+ movhlps m8, m2
+ punpcklbw m2, m9
+ punpcklbw m8, m9
+ pmaddwd m2, m6
+ pmaddwd m8, m6
+ packssdw m2, m8
+
+ movhlps m8, m7
+ punpcklbw m7, m9
+ punpcklbw m8, m9
+ pmaddwd m7, m5
+ pmaddwd m8, m5
+ packssdw m7, m8
+
+ paddw m2, m7
+
+ paddw m2, m4
+ psraw m2, 6
+ packuswb m2, m2
+ lea r2, [r2 + 2 * r3]
+ movd [r2], m2
+ pextrw r6d, m2, 2
+ mov [r2 + 4], r6w
+
+ movq m2, [r0 + 2 * r1]
+ punpcklbw m1, m2
+
+ movhlps m8, m3
+ punpcklbw m3, m9
+ punpcklbw m8, m9
+ pmaddwd m3, m6
+ pmaddwd m8, m6
+ packssdw m3, m8
+
+ movhlps m8, m1
+ punpcklbw m1, m9
+ punpcklbw m8, m9
+ pmaddwd m1, m5
+ pmaddwd m8, m5
+ packssdw m1, m8
+
+ paddw m3, m1
+
+ paddw m3, m4
+ psraw m3, 6
+ packuswb m3, m3
+
+ movd [r2 + r3], m3
+ pextrw r6d, m3, 2
+ mov [r2 + r3 + 4], r6w
+
+%if x < %1/4
+ lea r2, [r2 + 2 * r3]
+%endif
+%assign x x+1
+%endrep
+ RET
+
+%endmacro
+
+%if ARCH_X86_64
+ FILTER_V4_W6_H4_sse2 8
+ FILTER_V4_W6_H4_sse2 16
+%endif
+
+;-----------------------------------------------------------------------------
; void interp_4tap_horiz_pp_2x4(pixel *src, intptr_t srcStride, pixel *dst, intptr_t dstStride, int coeffIdx)
;-----------------------------------------------------------------------------
INIT_XMM sse4
diff -r 9ca14d0867a3 -r 6dc172cd4d9d source/common/x86/ipfilter8.h
--- a/source/common/x86/ipfilter8.h Fri May 08 13:34:34 2015 -0700
+++ b/source/common/x86/ipfilter8.h Fri May 08 13:43:25 2015 -0700
@@ -913,6 +913,10 @@
void x265_interp_4tap_vert_pp_4x8_sse2(const pixel *src, intptr_t srcStride, pixel *dst, intptr_t dstStride, int coeffIdx);
void x265_interp_4tap_vert_pp_4x16_sse2(const pixel *src, intptr_t srcStride, pixel *dst, intptr_t dstStride, int coeffIdx);
void x265_interp_4tap_vert_pp_4x32_sse2(const pixel *src, intptr_t srcStride, pixel *dst, intptr_t dstStride, int coeffIdx);
+#ifdef X86_64
+void x265_interp_4tap_vert_pp_6x8_sse2(const pixel *src, intptr_t srcStride, pixel *dst, intptr_t dstStride, int coeffIdx);
+void x265_interp_4tap_vert_pp_6x16_sse2(const pixel *src, intptr_t srcStride, pixel *dst, intptr_t dstStride, int coeffIdx);
+#endif
#undef LUMA_FILTERS
#undef LUMA_SP_FILTERS
#undef LUMA_SS_FILTERS
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