[x265] [PATCH 07 of 12] asm: interp_4tap_vert_ps_12xN sse2
dtyx265 at gmail.com
dtyx265 at gmail.com
Mon May 18 04:48:58 CEST 2015
# HG changeset patch
# User David T Yuen <dtyx265 at gmail.com>
# Date 1431914441 25200
# Node ID b6a91319ebe4a777f20a52a9d0ef801c087a19e2
# Parent 2a91f18790caee8c3b77838f04ae131acc2544b2
asm: interp_4tap_vert_ps_12xN sse2
Converted vert_pp_12xN macro to also create ps primitives. This replaces c code for ps with minimal impact on pp.
64-bit
./test/TestBench --testbench interp | grep vp | grep "12x"
chroma_vpp[12x16] 2.83x 8555.04 24230.19
chroma_vps[12x16] 2.29x 7875.15 18027.46
chroma_vpp[12x32] 2.87x 17085.12 49025.72
chroma_vps[12x32] 2.29x 15661.67 35787.46
chroma_vpp[12x16] 2.86x 8479.97 24229.99
chroma_vps[12x16] 2.32x 7757.38 18027.42
diff -r 2a91f18790ca -r b6a91319ebe4 source/common/x86/asm-primitives.cpp
--- a/source/common/x86/asm-primitives.cpp Sun May 17 18:53:44 2015 -0700
+++ b/source/common/x86/asm-primitives.cpp Sun May 17 19:00:41 2015 -0700
@@ -1527,16 +1527,19 @@
p.chroma[X265_CSP_I420].pu[CHROMA_420_8x8].filter_vps = x265_interp_4tap_vert_ps_8x8_sse2;
p.chroma[X265_CSP_I420].pu[CHROMA_420_8x16].filter_vps = x265_interp_4tap_vert_ps_8x16_sse2;
p.chroma[X265_CSP_I420].pu[CHROMA_420_8x32].filter_vps = x265_interp_4tap_vert_ps_8x32_sse2;
+ p.chroma[X265_CSP_I420].pu[CHROMA_420_12x16].filter_vps = x265_interp_4tap_vert_ps_12x16_sse2;
p.chroma[X265_CSP_I422].pu[CHROMA_422_6x16].filter_vps = x265_interp_4tap_vert_ps_6x16_sse2;
p.chroma[X265_CSP_I422].pu[CHROMA_422_8x8].filter_vps = x265_interp_4tap_vert_ps_8x8_sse2;
p.chroma[X265_CSP_I422].pu[CHROMA_422_8x12].filter_vps = x265_interp_4tap_vert_ps_8x12_sse2;
p.chroma[X265_CSP_I422].pu[CHROMA_422_8x16].filter_vps = x265_interp_4tap_vert_ps_8x16_sse2;
p.chroma[X265_CSP_I422].pu[CHROMA_422_8x32].filter_vps = x265_interp_4tap_vert_ps_8x32_sse2;
p.chroma[X265_CSP_I422].pu[CHROMA_422_8x64].filter_vps = x265_interp_4tap_vert_ps_8x64_sse2;
+ p.chroma[X265_CSP_I422].pu[CHROMA_422_12x32].filter_vps = x265_interp_4tap_vert_ps_12x32_sse2;
p.chroma[X265_CSP_I444].pu[LUMA_8x4].filter_vps = x265_interp_4tap_vert_ps_8x4_sse2;
p.chroma[X265_CSP_I444].pu[LUMA_8x8].filter_vps = x265_interp_4tap_vert_ps_8x8_sse2;
p.chroma[X265_CSP_I444].pu[LUMA_8x16].filter_vps = x265_interp_4tap_vert_ps_8x16_sse2;
p.chroma[X265_CSP_I444].pu[LUMA_8x32].filter_vps = x265_interp_4tap_vert_ps_8x32_sse2;
+ p.chroma[X265_CSP_I444].pu[LUMA_12x16].filter_vps = x265_interp_4tap_vert_ps_12x16_sse2;
#endif
ALL_LUMA_PU(luma_hpp, interp_8tap_horiz_pp, sse2);
diff -r 2a91f18790ca -r b6a91319ebe4 source/common/x86/ipfilter8.asm
--- a/source/common/x86/ipfilter8.asm Sun May 17 18:53:44 2015 -0700
+++ b/source/common/x86/ipfilter8.asm Sun May 17 19:00:41 2015 -0700
@@ -1900,16 +1900,22 @@
%endif
;-----------------------------------------------------------------------------
-; void interp_4tap_vert_pp_12xN(pixel *src, intptr_t srcStride, pixel *dst, intptr_t dstStride, int coeffIdx)
-;-----------------------------------------------------------------------------
-%macro FILTER_V4_W12_H2_sse2 1
+; void interp_4tap_vert_%1_12x%2(pixel *src, intptr_t srcStride, pixel *dst, intptr_t dstStride, int coeffIdx)
+;-----------------------------------------------------------------------------
+%macro FILTER_V4_W12_H2_sse2 2
INIT_XMM sse2
-cglobal interp_4tap_vert_pp_12x%1, 4, 6, 11
+cglobal interp_4tap_vert_%1_12x%2, 4, 6, 11
mov r4d, r4m
sub r0, r1
shl r4d, 5
pxor m9, m9
+
+%ifidn %1,pp
mova m6, [pw_32]
+%elifidn %1,ps
+ mova m6, [pw_2000]
+ add r3d, r3d
+%endif
%ifdef PIC
lea r5, [tab_ChromaCoeffV]
@@ -1921,7 +1927,7 @@
%endif
%assign x 1
-%rep %1/2
+%rep %2/2
movu m2, [r0]
movu m3, [r0 + r1]
@@ -1966,6 +1972,7 @@
paddw m2, m10
+%ifidn %1,pp
paddw m4, m6
psraw m4, 6
paddw m2, m6
@@ -1975,6 +1982,12 @@
movh [r2], m4
psrldq m4, 8
movd [r2 + 8], m4
+%elifidn %1,ps
+ psubw m4, m6
+ psubw m2, m6
+ movu [r2], m4
+ movh [r2 + 16], m2
+%endif
punpcklbw m4, m3, m5
punpckhbw m3, m5
@@ -2014,6 +2027,7 @@
paddw m4, m2
paddw m3, m7
+%ifidn %1,pp
paddw m4, m6
psraw m4, 6
paddw m3, m6
@@ -2023,8 +2037,14 @@
movh [r2 + r3], m4
psrldq m4, 8
movd [r2 + r3 + 8], m4
-
-%if x < %1/2
+%elifidn %1,ps
+ psubw m4, m6
+ psubw m3, m6
+ movu [r2 + r3], m4
+ movh [r2 + r3 + 16], m3
+%endif
+
+%if x < %2/2
lea r2, [r2 + 2 * r3]
%endif
%assign x x+1
@@ -2034,8 +2054,10 @@
%endmacro
%if ARCH_X86_64
- FILTER_V4_W12_H2_sse2 16
- FILTER_V4_W12_H2_sse2 32
+ FILTER_V4_W12_H2_sse2 pp, 16
+ FILTER_V4_W12_H2_sse2 pp, 32
+ FILTER_V4_W12_H2_sse2 ps, 16
+ FILTER_V4_W12_H2_sse2 ps, 32
%endif
;-----------------------------------------------------------------------------
diff -r 2a91f18790ca -r b6a91319ebe4 source/common/x86/ipfilter8.h
--- a/source/common/x86/ipfilter8.h Sun May 17 18:53:44 2015 -0700
+++ b/source/common/x86/ipfilter8.h Sun May 17 19:00:41 2015 -0700
@@ -964,6 +964,8 @@
void x265_interp_4tap_vert_ps_8x16_sse2(const pixel* src, intptr_t srcStride, int16_t* dst, intptr_t dstStride, int coeffIdx);
void x265_interp_4tap_vert_ps_8x32_sse2(const pixel* src, intptr_t srcStride, int16_t* dst, intptr_t dstStride, int coeffIdx);
void x265_interp_4tap_vert_ps_8x64_sse2(const pixel* src, intptr_t srcStride, int16_t* dst, intptr_t dstStride, int coeffIdx);
+void x265_interp_4tap_vert_ps_12x16_sse2(const pixel* src, intptr_t srcStride, int16_t* dst, intptr_t dstStride, int coeffIdx);
+void x265_interp_4tap_vert_ps_12x32_sse2(const pixel* src, intptr_t srcStride, int16_t* dst, intptr_t dstStride, int coeffIdx);
#endif
#undef LUMA_FILTERS
#undef LUMA_SP_FILTERS
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