[x265] [PATCH 08 of 12] asm: interp_4tap_vert_ps_16xN sse2
dtyx265 at gmail.com
dtyx265 at gmail.com
Mon May 18 04:48:59 CEST 2015
# HG changeset patch
# User David T Yuen <dtyx265 at gmail.com>
# Date 1431914811 25200
# Node ID f8333270d592d9ada2318fb3286ca884b13d3249
# Parent b6a91319ebe4a777f20a52a9d0ef801c087a19e2
asm: interp_4tap_vert_ps_16xN sse2
Converted vert_pp_16xN macro to also create ps primitives. This replaces c code for ps with minimal impact on pp.
64-bit
./test/TestBench --testbench interp | grep vp | grep "16x"
chroma_vpp[16x16] 3.90x 8256.30 32230.59
chroma_vps[16x16] 3.17x 7599.99 24104.14
chroma_vpp[ 16x8] 3.88x 4175.83 16187.80
chroma_vps[ 16x8] 3.11x 3840.00 11957.77
chroma_vpp[16x32] 3.93x 16435.21 64556.77
chroma_vps[16x32] 3.15x 15120.00 47622.26
chroma_vpp[16x12] 3.92x 6195.00 24270.27
chroma_vps[16x12] 3.14x 5720.05 17947.46
chroma_vpp[ 16x4] 3.86x 2115.00 8163.19
chroma_vps[ 16x4] 3.14x 1960.00 6160.84
chroma_vpp[16x32] 3.94x 16394.99 64530.13
chroma_vps[16x32] 3.13x 15120.04 47347.74
chroma_vpp[16x16] 3.91x 8235.00 32230.49
chroma_vps[16x16] 2.98x 7984.99 23827.91
chroma_vpp[16x64] 3.87x 33080.13 128135.33
chroma_vps[16x64] 3.09x 30613.33 94704.50
chroma_vpp[16x24] 3.94x 12315.02 48524.37
chroma_vps[16x24] 3.01x 11925.05 35897.88
chroma_vpp[ 16x8] 3.90x 4155.05 16187.66
chroma_vps[ 16x8] 2.96x 4044.99 11957.97
chroma_vpp[16x16] 3.80x 8475.00 32230.59
chroma_vps[16x16] 2.98x 7984.99 23827.48
chroma_vpp[ 16x8] 3.85x 4203.07 16187.50
chroma_vps[ 16x8] 3.11x 3840.00 11957.77
chroma_vpp[16x32] 3.81x 16922.52 64452.15
chroma_vps[16x32] 2.99x 15834.39 47348.57
chroma_vpp[16x12] 3.92x 6195.00 24269.99
chroma_vps[16x12] 3.06x 5858.04 17947.48
chroma_vpp[ 16x4] 3.86x 2115.00 8163.27
chroma_vps[ 16x4] 3.14x 1960.00 6152.63
chroma_vpp[16x64] 3.80x 33771.68 128367.91
chroma_vps[16x64] 2.99x 31614.99 94669.76
diff -r b6a91319ebe4 -r f8333270d592 source/common/x86/asm-primitives.cpp
--- a/source/common/x86/asm-primitives.cpp Sun May 17 19:00:41 2015 -0700
+++ b/source/common/x86/asm-primitives.cpp Sun May 17 19:06:51 2015 -0700
@@ -1528,6 +1528,11 @@
p.chroma[X265_CSP_I420].pu[CHROMA_420_8x16].filter_vps = x265_interp_4tap_vert_ps_8x16_sse2;
p.chroma[X265_CSP_I420].pu[CHROMA_420_8x32].filter_vps = x265_interp_4tap_vert_ps_8x32_sse2;
p.chroma[X265_CSP_I420].pu[CHROMA_420_12x16].filter_vps = x265_interp_4tap_vert_ps_12x16_sse2;
+ p.chroma[X265_CSP_I420].pu[CHROMA_420_16x4].filter_vps = x265_interp_4tap_vert_ps_16x4_sse2;
+ p.chroma[X265_CSP_I420].pu[CHROMA_420_16x8].filter_vps = x265_interp_4tap_vert_ps_16x8_sse2;
+ p.chroma[X265_CSP_I420].pu[CHROMA_420_16x12].filter_vps = x265_interp_4tap_vert_ps_16x12_sse2;
+ p.chroma[X265_CSP_I420].pu[CHROMA_420_16x16].filter_vps = x265_interp_4tap_vert_ps_16x16_sse2;
+ p.chroma[X265_CSP_I420].pu[CHROMA_420_16x32].filter_vps = x265_interp_4tap_vert_ps_16x32_sse2;
p.chroma[X265_CSP_I422].pu[CHROMA_422_6x16].filter_vps = x265_interp_4tap_vert_ps_6x16_sse2;
p.chroma[X265_CSP_I422].pu[CHROMA_422_8x8].filter_vps = x265_interp_4tap_vert_ps_8x8_sse2;
p.chroma[X265_CSP_I422].pu[CHROMA_422_8x12].filter_vps = x265_interp_4tap_vert_ps_8x12_sse2;
@@ -1535,11 +1540,22 @@
p.chroma[X265_CSP_I422].pu[CHROMA_422_8x32].filter_vps = x265_interp_4tap_vert_ps_8x32_sse2;
p.chroma[X265_CSP_I422].pu[CHROMA_422_8x64].filter_vps = x265_interp_4tap_vert_ps_8x64_sse2;
p.chroma[X265_CSP_I422].pu[CHROMA_422_12x32].filter_vps = x265_interp_4tap_vert_ps_12x32_sse2;
+ p.chroma[X265_CSP_I422].pu[CHROMA_422_16x8].filter_vps = x265_interp_4tap_vert_ps_16x8_sse2;
+ p.chroma[X265_CSP_I422].pu[CHROMA_422_16x16].filter_vps = x265_interp_4tap_vert_ps_16x16_sse2;
+ p.chroma[X265_CSP_I422].pu[CHROMA_422_16x24].filter_vps = x265_interp_4tap_vert_ps_16x24_sse2;
+ p.chroma[X265_CSP_I422].pu[CHROMA_422_16x32].filter_vps = x265_interp_4tap_vert_ps_16x32_sse2;
+ p.chroma[X265_CSP_I422].pu[CHROMA_422_16x64].filter_vps = x265_interp_4tap_vert_ps_16x64_sse2;
p.chroma[X265_CSP_I444].pu[LUMA_8x4].filter_vps = x265_interp_4tap_vert_ps_8x4_sse2;
p.chroma[X265_CSP_I444].pu[LUMA_8x8].filter_vps = x265_interp_4tap_vert_ps_8x8_sse2;
p.chroma[X265_CSP_I444].pu[LUMA_8x16].filter_vps = x265_interp_4tap_vert_ps_8x16_sse2;
p.chroma[X265_CSP_I444].pu[LUMA_8x32].filter_vps = x265_interp_4tap_vert_ps_8x32_sse2;
p.chroma[X265_CSP_I444].pu[LUMA_12x16].filter_vps = x265_interp_4tap_vert_ps_12x16_sse2;
+ p.chroma[X265_CSP_I444].pu[LUMA_16x4].filter_vps = x265_interp_4tap_vert_ps_16x4_sse2;
+ p.chroma[X265_CSP_I444].pu[LUMA_16x8].filter_vps = x265_interp_4tap_vert_ps_16x8_sse2;
+ p.chroma[X265_CSP_I444].pu[LUMA_16x12].filter_vps = x265_interp_4tap_vert_ps_16x12_sse2;
+ p.chroma[X265_CSP_I444].pu[LUMA_16x16].filter_vps = x265_interp_4tap_vert_ps_16x16_sse2;
+ p.chroma[X265_CSP_I444].pu[LUMA_16x32].filter_vps = x265_interp_4tap_vert_ps_16x32_sse2;
+ p.chroma[X265_CSP_I444].pu[LUMA_16x64].filter_vps = x265_interp_4tap_vert_ps_16x64_sse2;
#endif
ALL_LUMA_PU(luma_hpp, interp_8tap_horiz_pp, sse2);
diff -r b6a91319ebe4 -r f8333270d592 source/common/x86/ipfilter8.asm
--- a/source/common/x86/ipfilter8.asm Sun May 17 19:00:41 2015 -0700
+++ b/source/common/x86/ipfilter8.asm Sun May 17 19:06:51 2015 -0700
@@ -2061,16 +2061,22 @@
%endif
;-----------------------------------------------------------------------------
-; void interp_4tap_vert_pp_16xN(pixel *src, intptr_t srcStride, pixel *dst, intptr_t dstStride, int coeffIdx)
-;-----------------------------------------------------------------------------
-%macro FILTER_V4_W16_H2_sse2 1
+; void interp_4tap_vert_%1_16x%2(pixel *src, intptr_t srcStride, pixel *dst, intptr_t dstStride, int coeffIdx)
+;-----------------------------------------------------------------------------
+%macro FILTER_V4_W16_H2_sse2 2
INIT_XMM sse2
-cglobal interp_4tap_vert_pp_16x%1, 4, 6, 11
+cglobal interp_4tap_vert_%1_16x%2, 4, 6, 11
mov r4d, r4m
sub r0, r1
shl r4d, 5
pxor m9, m9
+
+%ifidn %1,pp
mova m6, [pw_32]
+%elifidn %1,ps
+ mova m6, [pw_2000]
+ add r3d, r3d
+%endif
%ifdef PIC
lea r5, [tab_ChromaCoeffV]
@@ -2082,7 +2088,7 @@
%endif
%assign x 1
-%rep %1/2
+%rep %2/2
movu m2, [r0]
movu m3, [r0 + r1]
@@ -2125,6 +2131,7 @@
packssdw m7, m8
paddw m4, m7
+%ifidn %1,pp
paddw m4, m6
psraw m4, 6
paddw m2, m6
@@ -2132,6 +2139,12 @@
packuswb m4, m2
movu [r2], m4
+%elifidn %1,ps
+ psubw m4, m6
+ psubw m2, m6
+ movu [r2], m4
+ movu [r2 + 16], m2
+%endif
punpcklbw m4, m3, m5
punpckhbw m3, m5
@@ -2172,15 +2185,22 @@
paddw m4, m2
paddw m3, m10
+%ifidn %1,pp
paddw m4, m6
psraw m4, 6
paddw m3, m6
psraw m3, 6
packuswb m4, m3
-
movu [r2 + r3], m4
-%if x < %1/2
+%elifidn %1,ps
+ psubw m4, m6
+ psubw m3, m6
+ movu [r2 + r3], m4
+ movu [r2 + r3 + 16], m3
+%endif
+
+%if x < %2/2
lea r2, [r2 + 2 * r3]
%endif
%assign x x+1
@@ -2190,14 +2210,23 @@
%endmacro
%if ARCH_X86_64
- FILTER_V4_W16_H2_sse2 4
- FILTER_V4_W16_H2_sse2 8
- FILTER_V4_W16_H2_sse2 12
- FILTER_V4_W16_H2_sse2 16
- FILTER_V4_W16_H2_sse2 32
-
- FILTER_V4_W16_H2_sse2 24
- FILTER_V4_W16_H2_sse2 64
+ FILTER_V4_W16_H2_sse2 pp, 4
+ FILTER_V4_W16_H2_sse2 pp, 8
+ FILTER_V4_W16_H2_sse2 pp, 12
+ FILTER_V4_W16_H2_sse2 pp, 16
+ FILTER_V4_W16_H2_sse2 pp, 32
+
+ FILTER_V4_W16_H2_sse2 pp, 24
+ FILTER_V4_W16_H2_sse2 pp, 64
+
+ FILTER_V4_W16_H2_sse2 ps, 4
+ FILTER_V4_W16_H2_sse2 ps, 8
+ FILTER_V4_W16_H2_sse2 ps, 12
+ FILTER_V4_W16_H2_sse2 ps, 16
+ FILTER_V4_W16_H2_sse2 ps, 32
+
+ FILTER_V4_W16_H2_sse2 ps, 24
+ FILTER_V4_W16_H2_sse2 ps, 64
%endif
;-----------------------------------------------------------------------------
diff -r b6a91319ebe4 -r f8333270d592 source/common/x86/ipfilter8.h
--- a/source/common/x86/ipfilter8.h Sun May 17 19:00:41 2015 -0700
+++ b/source/common/x86/ipfilter8.h Sun May 17 19:06:51 2015 -0700
@@ -966,6 +966,13 @@
void x265_interp_4tap_vert_ps_8x64_sse2(const pixel* src, intptr_t srcStride, int16_t* dst, intptr_t dstStride, int coeffIdx);
void x265_interp_4tap_vert_ps_12x16_sse2(const pixel* src, intptr_t srcStride, int16_t* dst, intptr_t dstStride, int coeffIdx);
void x265_interp_4tap_vert_ps_12x32_sse2(const pixel* src, intptr_t srcStride, int16_t* dst, intptr_t dstStride, int coeffIdx);
+void x265_interp_4tap_vert_ps_16x4_sse2(const pixel* src, intptr_t srcStride, int16_t* dst, intptr_t dstStride, int coeffIdx);
+void x265_interp_4tap_vert_ps_16x8_sse2(const pixel* src, intptr_t srcStride, int16_t* dst, intptr_t dstStride, int coeffIdx);
+void x265_interp_4tap_vert_ps_16x12_sse2(const pixel* src, intptr_t srcStride, int16_t* dst, intptr_t dstStride, int coeffIdx);
+void x265_interp_4tap_vert_ps_16x16_sse2(const pixel* src, intptr_t srcStride, int16_t* dst, intptr_t dstStride, int coeffIdx);
+void x265_interp_4tap_vert_ps_16x24_sse2(const pixel* src, intptr_t srcStride, int16_t* dst, intptr_t dstStride, int coeffIdx);
+void x265_interp_4tap_vert_ps_16x32_sse2(const pixel* src, intptr_t srcStride, int16_t* dst, intptr_t dstStride, int coeffIdx);
+void x265_interp_4tap_vert_ps_16x64_sse2(const pixel* src, intptr_t srcStride, int16_t* dst, intptr_t dstStride, int coeffIdx);
#endif
#undef LUMA_FILTERS
#undef LUMA_SP_FILTERS
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