[x265] [PATCH 02 of 12] asm: interp_4tap_vert_ps_4x2 sse2

[chen]

At 2015-05-18 10:48:53,dtyx265 at gmail.com wrote:
># HG changeset patch
># User David T Yuen <dtyx265 at gmail.com>
># Date 1431911615 25200
># Node ID 72bba6b9e99739599d040000be62c7e02a3c8faa
># Parent  465fb4340a241e501b53a6241f5ae81c29ba073a
>asm: interp_4tap_vert_ps_4x2 sse2
>
>Converted vert_pp_4x2 primitive to macro that also creates ps.  This replaces c code for ps with minimal impact on pp.
>
>64-bit
>
>/test/TestBench --testbench interp | grep vp | grep " 4x2"
>chroma_vpp[  4x2]	2.13x 	 524.99   	 1117.40
>chroma_vps[  4x2]	1.87x 	 457.54   	 854.98
>
>32-bit
>
>./test/TestBench --testbench interp | grep vp | grep " 4x2"
>chroma_vpp[  4x2]	2.34x 	 592.50   	 1387.29
>chroma_vps[  4x2]	2.41x 	 542.48   	 1304.96
>
>diff -r 465fb4340a24 -r 72bba6b9e997 source/common/x86/asm-primitives.cpp
>--- a/source/common/x86/asm-primitives.cpp	Sun May 17 18:03:29 2015 -0700
>+++ b/source/common/x86/asm-primitives.cpp	Sun May 17 18:13:35 2015 -0700
>@@ -1450,6 +1450,7 @@
>         p.chroma[X265_CSP_I444].pu[LUMA_4x16].filter_vpp = x265_interp_4tap_vert_pp_4x16_sse2;
>         p.chroma[X265_CSP_I420].pu[CHROMA_420_2x4].filter_vps = x265_interp_4tap_vert_ps_2x4_sse2;
>         p.chroma[X265_CSP_I420].pu[CHROMA_420_2x8].filter_vps = x265_interp_4tap_vert_ps_2x8_sse2;
>+        p.chroma[X265_CSP_I420].pu[CHROMA_420_4x2].filter_vps = x265_interp_4tap_vert_ps_4x2_sse2;
>         p.chroma[X265_CSP_I422].pu[CHROMA_422_2x16].filter_vps = x265_interp_4tap_vert_ps_2x16_sse2;
> #if X86_64
>         p.chroma[X265_CSP_I420].pu[CHROMA_420_6x8].filter_vpp = x265_interp_4tap_vert_pp_6x8_sse2;
>diff -r 465fb4340a24 -r 72bba6b9e997 source/common/x86/ipfilter8.asm
>--- a/source/common/x86/ipfilter8.asm	Sun May 17 18:03:29 2015 -0700
>+++ b/source/common/x86/ipfilter8.asm	Sun May 17 18:13:35 2015 -0700
>@@ -1025,11 +1025,11 @@
>     FILTER_V4_W2_H4_sse2 ps, 16
> 
> ;-----------------------------------------------------------------------------
>-; void interp_4tap_vert_pp_4x2(pixel *src, intptr_t srcStride, pixel *dst, intptr_t dstStride, int coeffIdx)
>-;-----------------------------------------------------------------------------
>+; void interp_4tap_vert_%1_4x2(pixel *src, intptr_t srcStride, pixel *dst, intptr_t dstStride, int coeffIdx)
>+;-----------------------------------------------------------------------------
>+%macro  FILTER_V2_W4_H4_sse2 1
> INIT_XMM sse2
>-cglobal interp_4tap_vert_pp_4x2, 4, 6, 8
>-
>+cglobal interp_4tap_vert_%1_4x2, 4, 6, 8
>     mov         r4d,       r4m
>     sub         r0,        r1
>     pxor        m7,        m7
>@@ -1078,6 +1078,8 @@
>     pshuflw     m5,        m3,        q2301
>     pshufhw     m5,        m5,        q2301
>     paddw       m3,        m5
>+
>+%ifidn %1, pp
>     psrld       m2,        16
>     psrld       m3,        16
>     packssdw    m2,        m3
>@@ -1089,7 +1091,24 @@
>     movd        [r2],      m2
>     psrldq      m2,        4
>     movd        [r2 + r3], m2
>-    RET
>+%elifidn %1, ps
>+    psrldq      m2,        2
>+    psrldq      m3,        2
>+    pshufd      m2,        m2, q3120
>+    pshufd      m3,        m3, q3120
>+    punpcklqdq  m2, m3
>+
>+    add         r3d,       r3d

unneed
>+    psubw       m2,        [pw_2000]
>+    movh        [r2],      m2
>+    movhps      [r2 + r3], m2

MOVHPS because above PUNPCKLQDQ, we didn't need combo and split, same count of instructions and slower on Intel CPU
>+%endif
>+    RET
>+
>+%endmacro
>+
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