[x265] [PATCH 06 of 12] asm: interp_4tap_vert_ps_8xN sse2
dtyx265 at gmail.com
dtyx265 at gmail.com
Tue May 19 02:24:33 CEST 2015
# HG changeset patch
# User David T Yuen <dtyx265 at gmail.com>
# Date 1431992999 25200
# Node ID 6a2fe809ba56b8f54de9d09603b57e6887735eab
# Parent e1d6fc3777bca3f72bf04367a345ad91124d0bc5
asm: interp_4tap_vert_ps_8xN sse2
Converted vert_pp_8xN macro to also create ps primitives. This replaces c code for ps with minimal impact on pp.
64-bit
./test/TestBench --testbench interp | grep vp | grep " 8x"
chroma_vpp[ 8x8] 4.10x 1997.48 8187.65
chroma_vps[ 8x8] 3.30x 1877.49 6197.81
chroma_vpp[ 8x16] 4.12x 3937.49 16230.29
chroma_vps[ 8x16] 3.30x 3732.49 12307.48
chroma_vpp[ 8x32] 4.13x 7829.99 32339.43
chroma_vps[ 8x32] 3.32x 7331.23 24308.07
chroma_vpp[ 8x16] 4.12x 3937.49 16230.63
chroma_vps[ 8x16] 3.31x 3713.11 12307.48
chroma_vpp[ 8x8] 4.10x 1997.48 8187.50
chroma_vps[ 8x8] 3.28x 1892.48 6205.51
chroma_vpp[ 8x32] 4.10x 7827.18 32070.29
chroma_vps[ 8x32] 3.33x 7375.95 24588.47
chroma_vpp[ 8x12] 4.11x 2985.00 12271.01
chroma_vps[ 8x12] 3.35x 2777.49 9308.00
chroma_vpp[ 8x64] 4.11x 15584.79 64033.62
chroma_vps[ 8x64] 3.30x 14733.18 48692.98
chroma_vpp[ 8x8] 4.07x 2010.00 8187.50
chroma_vps[ 8x8] 3.30x 1877.50 6197.78
chroma_vpp[ 8x16] 4.12x 3942.37 16230.14
chroma_vps[ 8x16] 3.31x 3718.03 12307.61
chroma_vpp[ 8x32] 4.10x 7817.48 32070.28
chroma_vps[ 8x32] 3.28x 7412.57 24307.81
diff -r e1d6fc3777bc -r 6a2fe809ba56 source/common/x86/asm-primitives.cpp
--- a/source/common/x86/asm-primitives.cpp Mon May 18 16:34:04 2015 -0700
+++ b/source/common/x86/asm-primitives.cpp Mon May 18 16:49:59 2015 -0700
@@ -1524,8 +1524,19 @@
p.chroma[X265_CSP_I420].pu[CHROMA_420_8x2].filter_vps = x265_interp_4tap_vert_ps_8x2_sse2;
p.chroma[X265_CSP_I420].pu[CHROMA_420_8x4].filter_vps = x265_interp_4tap_vert_ps_8x4_sse2;
p.chroma[X265_CSP_I420].pu[CHROMA_420_8x6].filter_vps = x265_interp_4tap_vert_ps_8x6_sse2;
+ p.chroma[X265_CSP_I420].pu[CHROMA_420_8x8].filter_vps = x265_interp_4tap_vert_ps_8x8_sse2;
+ p.chroma[X265_CSP_I420].pu[CHROMA_420_8x16].filter_vps = x265_interp_4tap_vert_ps_8x16_sse2;
+ p.chroma[X265_CSP_I420].pu[CHROMA_420_8x32].filter_vps = x265_interp_4tap_vert_ps_8x32_sse2;
p.chroma[X265_CSP_I422].pu[CHROMA_422_6x16].filter_vps = x265_interp_4tap_vert_ps_6x16_sse2;
+ p.chroma[X265_CSP_I422].pu[CHROMA_422_8x8].filter_vps = x265_interp_4tap_vert_ps_8x8_sse2;
+ p.chroma[X265_CSP_I422].pu[CHROMA_422_8x12].filter_vps = x265_interp_4tap_vert_ps_8x12_sse2;
+ p.chroma[X265_CSP_I422].pu[CHROMA_422_8x16].filter_vps = x265_interp_4tap_vert_ps_8x16_sse2;
+ p.chroma[X265_CSP_I422].pu[CHROMA_422_8x32].filter_vps = x265_interp_4tap_vert_ps_8x32_sse2;
+ p.chroma[X265_CSP_I422].pu[CHROMA_422_8x64].filter_vps = x265_interp_4tap_vert_ps_8x64_sse2;
p.chroma[X265_CSP_I444].pu[LUMA_8x4].filter_vps = x265_interp_4tap_vert_ps_8x4_sse2;
+ p.chroma[X265_CSP_I444].pu[LUMA_8x8].filter_vps = x265_interp_4tap_vert_ps_8x8_sse2;
+ p.chroma[X265_CSP_I444].pu[LUMA_8x16].filter_vps = x265_interp_4tap_vert_ps_8x16_sse2;
+ p.chroma[X265_CSP_I444].pu[LUMA_8x32].filter_vps = x265_interp_4tap_vert_ps_8x32_sse2;
#endif
ALL_LUMA_PU(luma_hpp, interp_8tap_horiz_pp, sse2);
diff -r e1d6fc3777bc -r 6a2fe809ba56 source/common/x86/ipfilter8.asm
--- a/source/common/x86/ipfilter8.asm Mon May 18 16:34:04 2015 -0700
+++ b/source/common/x86/ipfilter8.asm Mon May 18 16:49:59 2015 -0700
@@ -1721,12 +1721,11 @@
%endif
;-----------------------------------------------------------------------------
-; void interp_4tap_vert_pp_%1x%2(pixel *src, intptr_t srcStride, pixel *dst, intptr_t dstStride, int coeffIdx)
+; void interp_4tap_vert_%1_8x%2(pixel *src, intptr_t srcStride, pixel *dst, intptr_t dstStride, int coeffIdx)
;-----------------------------------------------------------------------------
%macro FILTER_V4_W8_H8_H16_H32_sse2 2
INIT_XMM sse2
-cglobal interp_4tap_vert_pp_%1x%2, 4, 6, 11
-
+cglobal interp_4tap_vert_%1_8x%2, 4, 6, 11
mov r4d, r4m
sub r0, r1
shl r4d, 5
@@ -1741,8 +1740,15 @@
mova m5, [tab_ChromaCoeff + r4 + 16]
%endif
+%ifidn %1,pp
mova m4, [pw_32]
+%elifidn %1,ps
+ mova m4, [pw_2000]
+ add r3d, r3d
+%endif
+
lea r5, [r1 * 3]
+ lea r4, [r3 * 3]
%assign x 1
%rep %2/4
@@ -1771,8 +1777,14 @@
packssdw m7, m8
paddw m0, m7
+
+%ifidn %1,pp
paddw m0, m4
psraw m0, 6
+%elifidn %1,ps
+ psubw m0, m4
+ movu [r2], m0
+%endif
lea r0, [r0 + 4 * r1]
movq m10, [r0]
@@ -1794,12 +1806,18 @@
packssdw m7, m8
paddw m1, m7
+
+%ifidn %1,pp
paddw m1, m4
psraw m1, 6
packuswb m0, m1
movh [r2], m0
movhps [r2 + r3], m0
+%elifidn %1,ps
+ psubw m1, m4
+ movu [r2 + r3], m1
+%endif
movq m1, [r0 + r1]
punpcklbw m10, m1
@@ -1819,8 +1837,14 @@
packssdw m10, m8
paddw m2, m10
+
+%ifidn %1,pp
paddw m2, m4
psraw m2, 6
+%elifidn %1,ps
+ psubw m2, m4
+ movu [r2 + 2 * r3], m2
+%endif
movq m7, [r0 + 2 * r1]
punpcklbw m1, m7
@@ -1840,27 +1864,40 @@
packssdw m1, m8
paddw m3, m1
+
+%ifidn %1,pp
paddw m3, m4
psraw m3, 6
packuswb m2, m3
- lea r2, [r2 + 2 * r3]
- movh [r2], m2
- movhps [r2 + r3], m2
+ movh [r2 + 2 * r3], m2
+ movhps [r2 + r4], m2
+%elifidn %1,ps
+ psubw m3, m4
+ movu [r2 + r4], m3
+%endif
+
%if x < %2/4
- lea r2, [r2 + 2 * r3]
+ lea r2, [r2 + 4 * r3]
%endif
%endrep
RET
%endmacro
%if ARCH_X86_64
- FILTER_V4_W8_H8_H16_H32_sse2 8, 8
- FILTER_V4_W8_H8_H16_H32_sse2 8, 16
- FILTER_V4_W8_H8_H16_H32_sse2 8, 32
-
- FILTER_V4_W8_H8_H16_H32_sse2 8, 12
- FILTER_V4_W8_H8_H16_H32_sse2 8, 64
+ FILTER_V4_W8_H8_H16_H32_sse2 pp, 8
+ FILTER_V4_W8_H8_H16_H32_sse2 pp, 16
+ FILTER_V4_W8_H8_H16_H32_sse2 pp, 32
+
+ FILTER_V4_W8_H8_H16_H32_sse2 pp, 12
+ FILTER_V4_W8_H8_H16_H32_sse2 pp, 64
+
+ FILTER_V4_W8_H8_H16_H32_sse2 ps, 8
+ FILTER_V4_W8_H8_H16_H32_sse2 ps, 16
+ FILTER_V4_W8_H8_H16_H32_sse2 ps, 32
+
+ FILTER_V4_W8_H8_H16_H32_sse2 ps, 12
+ FILTER_V4_W8_H8_H16_H32_sse2 ps, 64
%endif
;-----------------------------------------------------------------------------
diff -r e1d6fc3777bc -r 6a2fe809ba56 source/common/x86/ipfilter8.h
--- a/source/common/x86/ipfilter8.h Mon May 18 16:34:04 2015 -0700
+++ b/source/common/x86/ipfilter8.h Mon May 18 16:49:59 2015 -0700
@@ -959,6 +959,11 @@
void x265_interp_4tap_vert_ps_8x2_sse2(const pixel* src, intptr_t srcStride, int16_t* dst, intptr_t dstStride, int coeffIdx);
void x265_interp_4tap_vert_ps_8x4_sse2(const pixel* src, intptr_t srcStride, int16_t* dst, intptr_t dstStride, int coeffIdx);
void x265_interp_4tap_vert_ps_8x6_sse2(const pixel* src, intptr_t srcStride, int16_t* dst, intptr_t dstStride, int coeffIdx);
+void x265_interp_4tap_vert_ps_8x8_sse2(const pixel* src, intptr_t srcStride, int16_t* dst, intptr_t dstStride, int coeffIdx);
+void x265_interp_4tap_vert_ps_8x12_sse2(const pixel* src, intptr_t srcStride, int16_t* dst, intptr_t dstStride, int coeffIdx);
+void x265_interp_4tap_vert_ps_8x16_sse2(const pixel* src, intptr_t srcStride, int16_t* dst, intptr_t dstStride, int coeffIdx);
+void x265_interp_4tap_vert_ps_8x32_sse2(const pixel* src, intptr_t srcStride, int16_t* dst, intptr_t dstStride, int coeffIdx);
+void x265_interp_4tap_vert_ps_8x64_sse2(const pixel* src, intptr_t srcStride, int16_t* dst, intptr_t dstStride, int coeffIdx);
#endif
#undef LUMA_FILTERS
#undef LUMA_SP_FILTERS
More information about the x265-devel
mailing list