[x265] [PATCH 10 of 12] asm: interp_4tap_vert_ps_32xN sse2
dtyx265 at gmail.com
dtyx265 at gmail.com
Tue May 19 02:24:37 CEST 2015
# HG changeset patch
# User David T Yuen <dtyx265 at gmail.com>
# Date 1431994043 25200
# Node ID 91010ea886c50f9802c1ab872bd2648041137e19
# Parent a40fcb9a2fab1a4bd76e995b77a82779450e3082
asm: interp_4tap_vert_ps_32xN sse2
Converted vert_pp_32xN macro to also create ps primitives. This replaces c code for ps with minimal impact on pp.
64-bit
./test/TestBench --testbench interp | grep vp | grep "\[32x"
chroma_vpp[32x32] 8.08x 33708.93 272269.25
chroma_vps[32x32] 7.37x 30856.06 227457.75
chroma_vpp[32x16] 8.02x 16937.82 135783.27
chroma_vps[32x16] 7.40x 15547.49 115006.89
chroma_vpp[32x24] 7.98x 25323.07 202165.66
chroma_vps[32x24] 7.39x 23167.78 171095.48
chroma_vpp[32x64] 8.12x 67083.93 544483.62
chroma_vps[32x64] 7.40x 61465.67 454573.19
chroma_vpp[32x32] 8.09x 33677.42 272548.59
chroma_vps[32x32] 7.35x 30939.49 227262.39
chroma_vpp[32x48] 8.13x 50357.48 409341.44
chroma_vps[32x48] 7.34x 46383.85 340399.75
chroma_vpp[32x16] 8.08x 16937.50 136813.33
chroma_vps[32x16] 7.35x 15547.78 114306.04
chroma_vpp[32x32] 8.10x 33646.01 272573.78
chroma_vps[32x32] 7.36x 30866.95 227196.88
chroma_vpp[32x16] 8.03x 16937.63 136053.83
chroma_vps[32x16] 7.33x 15547.37 113901.99
chroma_vpp[32x64] 8.16x 67056.32 547280.69
chroma_vps[32x64] 7.39x 61463.44 454434.88
chroma_vpp[32x24] 8.05x 25326.60 203882.61
chroma_vps[32x24] 7.38x 23167.60 171023.12
diff -r a40fcb9a2fab -r 91010ea886c5 source/common/x86/asm-primitives.cpp
--- a/source/common/x86/asm-primitives.cpp Mon May 18 17:02:18 2015 -0700
+++ b/source/common/x86/asm-primitives.cpp Mon May 18 17:07:23 2015 -0700
@@ -1534,6 +1534,10 @@
p.chroma[X265_CSP_I420].pu[CHROMA_420_16x16].filter_vps = x265_interp_4tap_vert_ps_16x16_sse2;
p.chroma[X265_CSP_I420].pu[CHROMA_420_16x32].filter_vps = x265_interp_4tap_vert_ps_16x32_sse2;
p.chroma[X265_CSP_I420].pu[CHROMA_420_24x32].filter_vps = x265_interp_4tap_vert_ps_24x32_sse2;
+ p.chroma[X265_CSP_I420].pu[CHROMA_420_32x8].filter_vps = x265_interp_4tap_vert_ps_32x8_sse2;
+ p.chroma[X265_CSP_I420].pu[CHROMA_420_32x16].filter_vps = x265_interp_4tap_vert_ps_32x16_sse2;
+ p.chroma[X265_CSP_I420].pu[CHROMA_420_32x24].filter_vps = x265_interp_4tap_vert_ps_32x24_sse2;
+ p.chroma[X265_CSP_I420].pu[CHROMA_420_32x32].filter_vps = x265_interp_4tap_vert_ps_32x32_sse2;
p.chroma[X265_CSP_I422].pu[CHROMA_422_6x16].filter_vps = x265_interp_4tap_vert_ps_6x16_sse2;
p.chroma[X265_CSP_I422].pu[CHROMA_422_8x8].filter_vps = x265_interp_4tap_vert_ps_8x8_sse2;
p.chroma[X265_CSP_I422].pu[CHROMA_422_8x12].filter_vps = x265_interp_4tap_vert_ps_8x12_sse2;
@@ -1547,6 +1551,10 @@
p.chroma[X265_CSP_I422].pu[CHROMA_422_16x32].filter_vps = x265_interp_4tap_vert_ps_16x32_sse2;
p.chroma[X265_CSP_I422].pu[CHROMA_422_16x64].filter_vps = x265_interp_4tap_vert_ps_16x64_sse2;
p.chroma[X265_CSP_I422].pu[CHROMA_422_24x64].filter_vps = x265_interp_4tap_vert_ps_24x64_sse2;
+ p.chroma[X265_CSP_I422].pu[CHROMA_422_32x16].filter_vps = x265_interp_4tap_vert_ps_32x16_sse2;
+ p.chroma[X265_CSP_I422].pu[CHROMA_422_32x32].filter_vps = x265_interp_4tap_vert_ps_32x32_sse2;
+ p.chroma[X265_CSP_I422].pu[CHROMA_422_32x48].filter_vps = x265_interp_4tap_vert_ps_32x48_sse2;
+ p.chroma[X265_CSP_I422].pu[CHROMA_422_32x64].filter_vps = x265_interp_4tap_vert_ps_32x64_sse2;
p.chroma[X265_CSP_I444].pu[LUMA_8x4].filter_vps = x265_interp_4tap_vert_ps_8x4_sse2;
p.chroma[X265_CSP_I444].pu[LUMA_8x8].filter_vps = x265_interp_4tap_vert_ps_8x8_sse2;
p.chroma[X265_CSP_I444].pu[LUMA_8x16].filter_vps = x265_interp_4tap_vert_ps_8x16_sse2;
@@ -1559,6 +1567,11 @@
p.chroma[X265_CSP_I444].pu[LUMA_16x32].filter_vps = x265_interp_4tap_vert_ps_16x32_sse2;
p.chroma[X265_CSP_I444].pu[LUMA_16x64].filter_vps = x265_interp_4tap_vert_ps_16x64_sse2;
p.chroma[X265_CSP_I444].pu[LUMA_24x32].filter_vps = x265_interp_4tap_vert_ps_24x32_sse2;
+ p.chroma[X265_CSP_I444].pu[LUMA_32x8].filter_vps = x265_interp_4tap_vert_ps_32x8_sse2;
+ p.chroma[X265_CSP_I444].pu[LUMA_32x16].filter_vps = x265_interp_4tap_vert_ps_32x16_sse2;
+ p.chroma[X265_CSP_I444].pu[LUMA_32x24].filter_vps = x265_interp_4tap_vert_ps_32x24_sse2;
+ p.chroma[X265_CSP_I444].pu[LUMA_32x32].filter_vps = x265_interp_4tap_vert_ps_32x32_sse2;
+ p.chroma[X265_CSP_I444].pu[LUMA_32x64].filter_vps = x265_interp_4tap_vert_ps_32x64_sse2;
#endif
ALL_LUMA_PU(luma_hpp, interp_8tap_horiz_pp, sse2);
diff -r a40fcb9a2fab -r 91010ea886c5 source/common/x86/ipfilter8.asm
--- a/source/common/x86/ipfilter8.asm Mon May 18 17:02:18 2015 -0700
+++ b/source/common/x86/ipfilter8.asm Mon May 18 17:07:23 2015 -0700
@@ -2465,16 +2465,21 @@
%endif
;-----------------------------------------------------------------------------
-; void interp_4tap_vert_pp_32xN(pixel *src, intptr_t srcStride, pixel *dst, intptr_t dstStride, int coeffIdx)
-;-----------------------------------------------------------------------------
-%macro FILTER_V4_W32_sse2 1
+; void interp_4tap_vert_%1_32x%2(pixel *src, intptr_t srcStride, pixel *dst, intptr_t dstStride, int coeffIdx)
+;-----------------------------------------------------------------------------
+%macro FILTER_V4_W32_sse2 2
INIT_XMM sse2
-cglobal interp_4tap_vert_pp_32x%1, 4, 6, 10
+cglobal interp_4tap_vert_%1_32x%2, 4, 6, 10
mov r4d, r4m
sub r0, r1
shl r4d, 5
pxor m9, m9
+
+%ifidn %1,pp
mova m6, [pw_32]
+%elifidn %1,ps
+ mova m6, [pw_2000]
+%endif
%ifdef PIC
lea r5, [tab_ChromaCoeffV]
@@ -2485,7 +2490,7 @@
mova m0, [tab_ChromaCoeffV + r4 + 16]
%endif
- mov r4d, %1
+ mov r4d, %2
.loop:
movu m2, [r0]
@@ -2532,6 +2537,7 @@
paddw m4, m7
paddw m2, m3
+%ifidn %1,pp
paddw m4, m6
psraw m4, 6
paddw m2, m6
@@ -2539,6 +2545,12 @@
packuswb m4, m2
movu [r2], m4
+%elifidn %1,ps
+ psubw m4, m6
+ psubw m2, m6
+ movu [r2], m4
+ movu [r2 + 16], m2
+%endif
movu m2, [r0 + 16]
movu m3, [r0 + r1 + 16]
@@ -2583,6 +2595,7 @@
paddw m4, m7
paddw m2, m3
+%ifidn %1,pp
paddw m4, m6
psraw m4, 6
paddw m2, m6
@@ -2590,9 +2603,16 @@
packuswb m4, m2
movu [r2 + 16], m4
+ lea r2, [r2 + r3]
+%elifidn %1,ps
+ psubw m4, m6
+ psubw m2, m6
+ movu [r2 + 32], m4
+ movu [r2 + 48], m2
+ lea r2, [r2 + 2 * r3]
+%endif
lea r0, [r0 + r1]
- lea r2, [r2 + r3]
dec r4
jnz .loop
RET
@@ -2600,13 +2620,21 @@
%endmacro
%if ARCH_X86_64
- FILTER_V4_W32_sse2 8
- FILTER_V4_W32_sse2 16
- FILTER_V4_W32_sse2 24
- FILTER_V4_W32_sse2 32
-
- FILTER_V4_W32_sse2 48
- FILTER_V4_W32_sse2 64
+ FILTER_V4_W32_sse2 pp, 8
+ FILTER_V4_W32_sse2 pp, 16
+ FILTER_V4_W32_sse2 pp, 24
+ FILTER_V4_W32_sse2 pp, 32
+
+ FILTER_V4_W32_sse2 pp, 48
+ FILTER_V4_W32_sse2 pp, 64
+
+ FILTER_V4_W32_sse2 ps, 8
+ FILTER_V4_W32_sse2 ps, 16
+ FILTER_V4_W32_sse2 ps, 24
+ FILTER_V4_W32_sse2 ps, 32
+
+ FILTER_V4_W32_sse2 ps, 48
+ FILTER_V4_W32_sse2 ps, 64
%endif
;-----------------------------------------------------------------------------
diff -r a40fcb9a2fab -r 91010ea886c5 source/common/x86/ipfilter8.h
--- a/source/common/x86/ipfilter8.h Mon May 18 17:02:18 2015 -0700
+++ b/source/common/x86/ipfilter8.h Mon May 18 17:07:23 2015 -0700
@@ -975,6 +975,12 @@
void x265_interp_4tap_vert_ps_16x64_sse2(const pixel* src, intptr_t srcStride, int16_t* dst, intptr_t dstStride, int coeffIdx);
void x265_interp_4tap_vert_ps_24x32_sse2(const pixel* src, intptr_t srcStride, int16_t* dst, intptr_t dstStride, int coeffIdx);
void x265_interp_4tap_vert_ps_24x64_sse2(const pixel* src, intptr_t srcStride, int16_t* dst, intptr_t dstStride, int coeffIdx);
+void x265_interp_4tap_vert_ps_32x8_sse2(const pixel* src, intptr_t srcStride, int16_t* dst, intptr_t dstStride, int coeffIdx);
+void x265_interp_4tap_vert_ps_32x16_sse2(const pixel* src, intptr_t srcStride, int16_t* dst, intptr_t dstStride, int coeffIdx);
+void x265_interp_4tap_vert_ps_32x24_sse2(const pixel* src, intptr_t srcStride, int16_t* dst, intptr_t dstStride, int coeffIdx);
+void x265_interp_4tap_vert_ps_32x32_sse2(const pixel* src, intptr_t srcStride, int16_t* dst, intptr_t dstStride, int coeffIdx);
+void x265_interp_4tap_vert_ps_32x48_sse2(const pixel* src, intptr_t srcStride, int16_t* dst, intptr_t dstStride, int coeffIdx);
+void x265_interp_4tap_vert_ps_32x64_sse2(const pixel* src, intptr_t srcStride, int16_t* dst, intptr_t dstStride, int coeffIdx);
#endif
#undef LUMA_FILTERS
#undef LUMA_SP_FILTERS
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