[x265] [PATCH 102 of 307] x86: AVX512 interp_4tap_horiz_pp_32xN for high bit depth
mythreyi at multicorewareinc.com
mythreyi at multicorewareinc.com
Sat Apr 7 04:31:40 CEST 2018
# HG changeset patch
# User Vignesh Vijayakumar
# Date 1504160499 -19800
# Thu Aug 31 11:51:39 2017 +0530
# Node ID a98d83b53b2e32b4060b05342ee041c44eff2045
# Parent 1a31df496144c526fd5eba9d960bb286a81ae2d5
x86: AVX512 interp_4tap_horiz_pp_32xN for high bit depth
i444
Size | AVX2 performance | AVX512 performance
----------------------------------------------
32x8 | 7.05x | 22.91x
32x16 | 7.15x | 22.19x
32x24 | 7.27x | 21.79x
32x32 | 7.16x | 22.09x
32x64 | 7.41x | 21.72x
diff -r 1a31df496144 -r a98d83b53b2e source/common/x86/asm-primitives.cpp
--- a/source/common/x86/asm-primitives.cpp Thu Apr 05 14:14:28 2018 -0700
+++ b/source/common/x86/asm-primitives.cpp Thu Aug 31 11:51:39 2017 +0530
@@ -2354,6 +2354,22 @@
p.cu[BLOCK_32x32].copy_cnt = PFX(copy_cnt_32_avx512);
p.cu[BLOCK_16x16].copy_cnt = PFX(copy_cnt_16_avx512);
+ p.chroma[X265_CSP_I420].pu[CHROMA_420_32x8].filter_hpp = PFX(interp_4tap_horiz_pp_32x8_avx512);
+ p.chroma[X265_CSP_I420].pu[CHROMA_420_32x16].filter_hpp = PFX(interp_4tap_horiz_pp_32x16_avx512);
+ p.chroma[X265_CSP_I420].pu[CHROMA_420_32x24].filter_hpp = PFX(interp_4tap_horiz_pp_32x24_avx512);
+ p.chroma[X265_CSP_I420].pu[CHROMA_420_32x32].filter_hpp = PFX(interp_4tap_horiz_pp_32x32_avx512);
+
+ p.chroma[X265_CSP_I422].pu[CHROMA_422_32x16].filter_hpp = PFX(interp_4tap_horiz_pp_32x16_avx512);
+ p.chroma[X265_CSP_I422].pu[CHROMA_422_32x32].filter_hpp = PFX(interp_4tap_horiz_pp_32x32_avx512);
+ p.chroma[X265_CSP_I422].pu[CHROMA_422_32x48].filter_hpp = PFX(interp_4tap_horiz_pp_32x48_avx512);
+ p.chroma[X265_CSP_I422].pu[CHROMA_422_32x64].filter_hpp = PFX(interp_4tap_horiz_pp_32x64_avx512);
+
+ p.chroma[X265_CSP_I444].pu[LUMA_32x8].filter_hpp = PFX(interp_4tap_horiz_pp_32x8_avx512);
+ p.chroma[X265_CSP_I444].pu[LUMA_32x16].filter_hpp = PFX(interp_4tap_horiz_pp_32x16_avx512);
+ p.chroma[X265_CSP_I444].pu[LUMA_32x24].filter_hpp = PFX(interp_4tap_horiz_pp_32x24_avx512);
+ p.chroma[X265_CSP_I444].pu[LUMA_32x32].filter_hpp = PFX(interp_4tap_horiz_pp_32x32_avx512);
+ p.chroma[X265_CSP_I444].pu[LUMA_32x64].filter_hpp = PFX(interp_4tap_horiz_pp_32x64_avx512);
+
}
}
#else // if HIGH_BIT_DEPTH
diff -r 1a31df496144 -r a98d83b53b2e source/common/x86/ipfilter16.asm
--- a/source/common/x86/ipfilter16.asm Thu Apr 05 14:14:28 2018 -0700
+++ b/source/common/x86/ipfilter16.asm Thu Aug 31 11:51:39 2017 +0530
@@ -45,7 +45,7 @@
%endif
-SECTION_RODATA 32
+SECTION_RODATA 64
tab_c_524800: times 4 dd 524800
tab_c_n8192: times 8 dw -8192
@@ -106,6 +106,12 @@
times 8 dw 58, -10
times 8 dw 4, -1
+const interp8_hpp_shuf1_load_avx512, times 2 db 0, 1, 2, 3, 4, 5, 6, 7, 2, 3, 4, 5, 6, 7, 8, 9
+
+const interp8_hpp_shuf2_load_avx512, times 2 db 4, 5, 6, 7, 8, 9, 10, 11, 6, 7, 8, 9, 10, 11, 12, 13
+
+const interp8_hpp_shuf1_store_avx512, times 2 db 0, 1, 4, 5, 2, 3, 6, 7, 8, 9, 12, 13, 10, 11, 14, 15
+
SECTION .text
cextern pd_8
cextern pd_32
@@ -5073,3 +5079,106 @@
jnz .loop
RET
+;-------------------------------------------------------------------------------------------------------------
+;ipfilter_chroma_avx512 code start
+;-------------------------------------------------------------------------------------------------------------
+%macro PROCESS_IPFILTER_CHROMA_PP_32x2_AVX512 0
+ ; register map
+ ; m0 , m1 interpolate coeff
+ ; m2 , m3 shuffle order table
+ ; m4 - pd_32
+ ; m5 - zero
+ ; m6 - pw_pixel_max
+
+ movu m7, [r0]
+ movu m8, [r0 + 8]
+
+ pshufb m9, m7, m3
+ pshufb m7, m2
+ pmaddwd m7, m0
+ pmaddwd m9, m1
+ paddd m7, m9
+ paddd m7, m4
+ psrad m7, 6
+
+ pshufb m9, m8, m3
+ pshufb m8, m2
+ pmaddwd m8, m0
+ pmaddwd m9, m1
+ paddd m8, m9
+ paddd m8, m4
+ psrad m8, 6
+
+ packusdw m7, m8
+ CLIPW m7, m5, m6
+ pshufb m7, m10
+ movu [r2], m7
+
+ movu m7, [r0 + r1]
+ movu m8, [r0 + r1 + 8]
+
+ pshufb m9, m7, m3
+ pshufb m7, m2
+ pmaddwd m7, m0
+ pmaddwd m9, m1
+ paddd m7, m9
+ paddd m7, m4
+ psrad m7, 6
+
+ pshufb m9, m8, m3
+ pshufb m8, m2
+ pmaddwd m8, m0
+ pmaddwd m9, m1
+ paddd m8, m9
+ paddd m8, m4
+ psrad m8, 6
+
+ packusdw m7, m8
+ CLIPW m7, m5, m6
+ pshufb m7, m10
+ movu [r2 + r3], m7
+%endmacro
+
+;-------------------------------------------------------------------------------------------------------------
+; void interp_4tap_horiz_pp(pixel *src, intptr_t srcStride, int16_t *dst, intptr_t dstStride, int coeffIdx
+;-------------------------------------------------------------------------------------------------------------
+INIT_ZMM avx512
+%macro IPFILTER_CHROMA_AVX512_32xN 1
+cglobal interp_4tap_horiz_pp_32x%1, 5,6,11
+ add r1d, r1d
+ add r3d, r3d
+ sub r0, 2
+ mov r4d, r4m
+%ifdef PIC
+ lea r5, [tab_ChromaCoeff]
+ vpbroadcastd m0, [r5 + r4 * 8]
+ vpbroadcastd m1, [r5 + r4 * 8 + 4]
+%else
+ vpbroadcastd m0, [tab_ChromaCoeff + r4 * 8]
+ vpbroadcastd m1, [tab_ChromaCoeff + r4 * 8 + 4]
+%endif
+ vbroadcasti32x8 m2, [interp8_hpp_shuf1_load_avx512]
+ vbroadcasti32x8 m3, [interp8_hpp_shuf2_load_avx512]
+ vbroadcasti32x8 m4, [pd_32]
+ pxor m5, m5
+ vbroadcasti32x8 m6, [pw_pixel_max]
+ vbroadcasti32x8 m10, [interp8_hpp_shuf1_store_avx512]
+
+%rep %1/2 - 1
+ PROCESS_IPFILTER_CHROMA_PP_32x2_AVX512
+ lea r0, [r0 + 2 * r1]
+ lea r2, [r2 + 2 * r3]
+%endrep
+ PROCESS_IPFILTER_CHROMA_PP_32x2_AVX512
+ RET
+%endmacro
+
+IPFILTER_CHROMA_AVX512_32xN 8
+IPFILTER_CHROMA_AVX512_32xN 16
+IPFILTER_CHROMA_AVX512_32xN 24
+IPFILTER_CHROMA_AVX512_32xN 32
+IPFILTER_CHROMA_AVX512_32xN 48
+IPFILTER_CHROMA_AVX512_32xN 64
+;-------------------------------------------------------------------------------------------------------------
+;ipfilter_chroma_avx512 code end
+;-------------------------------------------------------------------------------------------------------------
\ No newline at end of file
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