[x265] [PATCH 144 of 307] x86: AVX512 interp_4tap_vert_pp_16xN for high bit depth
mythreyi at multicorewareinc.com
mythreyi at multicorewareinc.com
Sat Apr 7 04:32:22 CEST 2018
# HG changeset patch
# User Vignesh Vijayakumar<vignesh at multicorewareinc.com>
# Date 1509611825 -19800
# Thu Nov 02 14:07:05 2017 +0530
# Node ID ba385c1b80c649750ce66dda40a6364d50230b34
# Parent 75fb26372fc64e057c467625e79235c7dedb13c5
x86: AVX512 interp_4tap_vert_pp_16xN for high bit depth
i444
Size | AVX2 performance | AVX512 performance
----------------------------------------------
16x4 | 21.58x | 35.08x
16x8 | 25.33x | 33.51x
16x12 | 26.61x | 34.24x
16x16 | 26.87x | 35.28x
16x32 | 26.12x | 33.95x
16x64 | 27.36x | 34.98x
diff -r 75fb26372fc6 -r ba385c1b80c6 source/common/x86/asm-primitives.cpp
--- a/source/common/x86/asm-primitives.cpp Tue Oct 31 12:31:37 2017 +0530
+++ b/source/common/x86/asm-primitives.cpp Thu Nov 02 14:07:05 2017 +0530
@@ -2644,14 +2644,30 @@
p.chroma[X265_CSP_I444].pu[LUMA_32x24].filter_vpp = PFX(interp_4tap_vert_pp_32x24_avx512);
p.chroma[X265_CSP_I444].pu[LUMA_32x32].filter_vpp = PFX(interp_4tap_vert_pp_32x32_avx512);
p.chroma[X265_CSP_I444].pu[LUMA_32x64].filter_vpp = PFX(interp_4tap_vert_pp_32x64_avx512);
+ p.chroma[X265_CSP_I444].pu[LUMA_16x4].filter_vpp = PFX(interp_4tap_vert_pp_16x4_avx512);
+ p.chroma[X265_CSP_I444].pu[LUMA_16x8].filter_vpp = PFX(interp_4tap_vert_pp_16x8_avx512);
+ p.chroma[X265_CSP_I444].pu[LUMA_16x12].filter_vpp = PFX(interp_4tap_vert_pp_16x12_avx512);
+ p.chroma[X265_CSP_I444].pu[LUMA_16x16].filter_vpp = PFX(interp_4tap_vert_pp_16x16_avx512);
+ p.chroma[X265_CSP_I444].pu[LUMA_16x32].filter_vpp = PFX(interp_4tap_vert_pp_16x32_avx512);
+ p.chroma[X265_CSP_I444].pu[LUMA_16x64].filter_vpp = PFX(interp_4tap_vert_pp_16x64_avx512);
p.chroma[X265_CSP_I422].pu[CHROMA_422_32x16].filter_vpp = PFX(interp_4tap_vert_pp_32x16_avx512);
p.chroma[X265_CSP_I422].pu[CHROMA_422_32x32].filter_vpp = PFX(interp_4tap_vert_pp_32x32_avx512);
p.chroma[X265_CSP_I422].pu[CHROMA_422_32x48].filter_vpp = PFX(interp_4tap_vert_pp_32x48_avx512);
p.chroma[X265_CSP_I422].pu[CHROMA_422_32x64].filter_vpp = PFX(interp_4tap_vert_pp_32x64_avx512);
+ p.chroma[X265_CSP_I422].pu[CHROMA_422_16x8].filter_vpp = PFX(interp_4tap_vert_pp_16x8_avx512);
+ p.chroma[X265_CSP_I422].pu[CHROMA_422_16x16].filter_vpp = PFX(interp_4tap_vert_pp_16x16_avx512);
+ p.chroma[X265_CSP_I422].pu[CHROMA_422_16x24].filter_vpp = PFX(interp_4tap_vert_pp_16x24_avx512);
+ p.chroma[X265_CSP_I422].pu[CHROMA_422_16x32].filter_vpp = PFX(interp_4tap_vert_pp_16x32_avx512);
+ p.chroma[X265_CSP_I422].pu[CHROMA_422_16x64].filter_vpp = PFX(interp_4tap_vert_pp_16x64_avx512);
p.chroma[X265_CSP_I420].pu[CHROMA_420_32x8].filter_vpp = PFX(interp_4tap_vert_pp_32x8_avx512);
p.chroma[X265_CSP_I420].pu[CHROMA_420_32x16].filter_vpp = PFX(interp_4tap_vert_pp_32x16_avx512);
p.chroma[X265_CSP_I420].pu[CHROMA_420_32x24].filter_vpp = PFX(interp_4tap_vert_pp_32x24_avx512);
p.chroma[X265_CSP_I420].pu[CHROMA_420_32x32].filter_vpp = PFX(interp_4tap_vert_pp_32x32_avx512);
+ p.chroma[X265_CSP_I420].pu[CHROMA_420_16x4].filter_vpp = PFX(interp_4tap_vert_pp_16x4_avx512);
+ p.chroma[X265_CSP_I420].pu[CHROMA_420_16x8].filter_vpp = PFX(interp_4tap_vert_pp_16x8_avx512);
+ p.chroma[X265_CSP_I420].pu[CHROMA_420_16x12].filter_vpp = PFX(interp_4tap_vert_pp_16x12_avx512);
+ p.chroma[X265_CSP_I420].pu[CHROMA_420_16x16].filter_vpp = PFX(interp_4tap_vert_pp_16x16_avx512);
+ p.chroma[X265_CSP_I420].pu[CHROMA_420_16x32].filter_vpp = PFX(interp_4tap_vert_pp_16x32_avx512);
p.cu[BLOCK_8x8].dct = PFX(dct8_avx512);
diff -r 75fb26372fc6 -r ba385c1b80c6 source/common/x86/ipfilter16.asm
--- a/source/common/x86/ipfilter16.asm Tue Oct 31 12:31:37 2017 +0530
+++ b/source/common/x86/ipfilter16.asm Thu Nov 02 14:07:05 2017 +0530
@@ -5904,6 +5904,124 @@
RET
%endif
+%macro PROCESS_CHROMA_VERT_PP_16x4_AVX512 0
+ movu ym1, [r0]
+ lea r6, [r0 + 2 * r1]
+ vinserti32x8 m1, [r6], 1
+ movu ym3, [r0 + r1]
+ vinserti32x8 m3, [r6 + r1], 1
+ punpcklwd m0, m1, m3
+ pmaddwd m0, [r5]
+ punpckhwd m1, m3
+ pmaddwd m1, [r5]
+
+ movu ym4, [r0 + 2 * r1]
+ vinserti32x8 m4, [r6 + 2 * r1], 1
+ punpcklwd m2, m3, m4
+ pmaddwd m2, [r5]
+ punpckhwd m3, m4
+ pmaddwd m3, [r5]
+
+ lea r0, [r0 + 2 * r1]
+ lea r6, [r6 + 2 * r1]
+
+ movu ym5, [r0 + r1]
+ vinserti32x8 m5, [r6 + r1], 1
+ punpcklwd m6, m4, m5
+ pmaddwd m6, [r5 + mmsize]
+ paddd m0, m6
+ punpckhwd m4, m5
+ pmaddwd m4, [r5 + mmsize]
+ paddd m1, m4
+
+ movu ym4, [r0 + 2 * r1]
+ vinserti32x8 m4, [r6 + 2 * r1], 1
+ punpcklwd m6, m5, m4
+ pmaddwd m6, [r5 + mmsize]
+ paddd m2, m6
+ punpckhwd m5, m4
+ pmaddwd m5, [r5 + mmsize]
+ paddd m3, m5
+
+ paddd m0, m7
+ paddd m1, m7
+ paddd m2, m7
+ paddd m3, m7
+
+ psrad m0, INTERP_SHIFT_PP
+ psrad m1, INTERP_SHIFT_PP
+ psrad m2, INTERP_SHIFT_PP
+ psrad m3, INTERP_SHIFT_PP
+
+ packssdw m0, m1
+ packssdw m2, m3
+ pxor m5, m5
+ CLIPW2 m0, m2, m5, m8
+ movu [r2], ym0
+ movu [r2 + r3], ym2
+ vextracti32x8 [r2 + 2 * r3], m0, 1
+ vextracti32x8 [r2 + r7], m2, 1
+%endmacro
+
+;-----------------------------------------------------------------------------------------------------------------
+; void interp_4tap_vert(int16_t *src, intptr_t srcStride, int16_t *dst, intptr_t dstStride, int coeffIdx)
+;-----------------------------------------------------------------------------------------------------------------
+%if ARCH_X86_64
+INIT_ZMM avx512
+cglobal interp_4tap_vert_pp_16x4, 5, 8, 9
+ add r1d, r1d
+ add r3d, r3d
+ sub r0, r1
+ shl r4d, 7
+
+%ifdef PIC
+ lea r5, [tab_ChromaCoeffV_avx512]
+ lea r5, [r5 + r4]
+%else
+ lea r5, [tab_ChromaCoeffV_avx512 + r4]
+%endif
+ vbroadcasti32x8 m7, [INTERP_OFFSET_PP]
+ vbroadcasti32x8 m8, [pw_pixel_max]
+ lea r7, [3 * r3]
+ PROCESS_CHROMA_VERT_PP_16x4_AVX512
+ RET
+%endif
+
+%macro FILTER_VER_PP_CHROMA_16xN_AVX512 1
+INIT_ZMM avx512
+cglobal interp_4tap_vert_pp_16x%1, 5, 8, 9
+ add r1d, r1d
+ add r3d, r3d
+ sub r0, r1
+ shl r4d, 7
+
+%ifdef PIC
+ lea r5, [tab_ChromaCoeffV_avx512]
+ lea r5, [r5 + r4]
+%else
+ lea r5, [tab_ChromaCoeffV_avx512 + r4]
+%endif
+ vbroadcasti32x8 m7, [INTERP_OFFSET_PP]
+ vbroadcasti32x8 m8, [pw_pixel_max]
+ lea r7, [3 * r3]
+%rep %1/4 - 1
+ PROCESS_CHROMA_VERT_PP_16x4_AVX512
+ lea r0, [r0 + 2 * r1]
+ lea r2, [r2 + 4 * r3]
+%endrep
+ PROCESS_CHROMA_VERT_PP_16x4_AVX512
+ RET
+%endmacro
+
+%if ARCH_X86_64
+FILTER_VER_PP_CHROMA_16xN_AVX512 8
+FILTER_VER_PP_CHROMA_16xN_AVX512 12
+FILTER_VER_PP_CHROMA_16xN_AVX512 16
+FILTER_VER_PP_CHROMA_16xN_AVX512 24
+FILTER_VER_PP_CHROMA_16xN_AVX512 32
+FILTER_VER_PP_CHROMA_16xN_AVX512 64
+%endif
+
%macro PROCESS_CHROMA_VERT_PP_32x2_AVX512 0
movu m1, [r0]
movu m3, [r0 + r1]
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